參數(shù)資料
型號: MAX6853AEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 顯示驅(qū)動器
英文描述: 2-Wire Interfaced, 5 x 7 Matrix Vacuum-Fluorescent Display Controller
中文描述: VACUUM FLUOR DISPLAY DRIVER, PDSO16
封裝: 0.150 INCH, 0.25 MM PITCH, MO-137, QSOP-16
文件頁數(shù): 9/35頁
文件大小: 489K
代理商: MAX6853AEE
MAX6853
2-Wire Interfaced, 5
7 Matrix Vacuum-
Fluorescent Display Controller
______________________________________________________________________________________
17
Intensity Register
Digital control of display brightness is provided by
pulse-width modulation of the tube blanking time, which
is controlled by the lower nibble of the intensity register
(Table 26). The modulator scales the VFBLANK output
in 15 steps from a minimum of 1/16 up to 15/16 of each
grid’s multiplex period (Figure 16). Figure 17 shows the
modulator behavior when the VFBLANK polarity regis-
ter is set to 0x00 (Table 27), so VFBLANK is high to dis-
able (blank) the display.
The minimum off-time period of a 1/16 multiplex period
(6.25s with OSC = 4MHz) is always at the start of the
multiplex cycle. This allows time for slow display drivers
to turn off, and slow display phosphors time to decay
between grids. Thus, image ghosting is avoided. If a
display has very slow phosphor, double the allowed
decay time by not using a 15/16 duty cycle.
VFBLANK Polarity Register
The VFBLANK polarity register sets the active level of
the VFBLANK output pin (Table 27).
No-Op Register
A write to the no-op register is ignored.
Display-Test and Device ID Register
Writing the display-test and device ID register switches
the drivers between one of two modes: normal and dis-
play test. Display-test mode turns all segments and
annunciators on and sets the duty cycle to 7/16 (half-
power) (Table 28).
Reading the display-test and device ID register returns
the MAX6853 device ID 0b0000 011 that identifies the
driver type, plus the display-test status in the LSB.
Output Shift-Limit Register
The output serial interface transfers display data from
the MAX6853 to the display driver. The serial interface
bit-stream output length is programmable up to 122
bits, which are labeled DD0–DD121. Set the number of
bits with the shift-limit register, address 0x0E. If the
shift-limit register is written with an out-of-range value
0x7A to 0xFF, then the value 0x79 is stored instead.
Table 29 shows the shift-limit register.
Output Map
The output map comprises 122 words of 7-bit RAM.
The output map data should be written when the
MAX6853 is configured after power-up. Table 30 shows
the output map RAM codes.
RAM15
RAM14
RAM13
RAM12
RAM11
RAM10
RAM09
RAM08
RAM07
RAM05
RAM04
RAM03
RAM02
RAM01
RAM00
RAM16
RAM17
RAM18
RAM19
RAM20
RAM21
RAM23
1111
1110
1101
1100
1011
1010
1001
1000
0111
RAM06
RAM22
0110
0101
0100
0011
0010
0001
0000
MSB
LSB
x000
x001
x010
x011
x100
x101
x110
x111
Table 9. Character Map
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