- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄229278 > MAX6853AEE (MAXIM INTEGRATED PRODUCTS INC) 2-Wire Interfaced, 5 x 7 Matrix Vacuum-Fluorescent Display Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | MAX6853AEE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 2-Wire Interfaced, 5 x 7 Matrix Vacuum-Fluorescent Display Controller |
| 中文描述： | VACUUM FLUOR DISPLAY DRIVER, PDSO16 |
| 封裝： | 0.150 INCH, 0.25 MM PITCH, MO-137, QSOP-16 |
| 文件頁(yè)數(shù)： | 5/35頁(yè) |
| 文件大小： | 489K |
| 代理商： | MAX6853AEE |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)
MAX6853
2-Wire Interfaced, 5
7 Matrix Vacuum-
Fluorescent Display Controller
______________________________________________________________________________________
13
Global Blink Timing Synchronization
(T Data Bit D4) Format
Setting the T bit in multiple MAX6853s at the same time
(or in quick succession) synchronizes the blink timing
across all the devices (Table 21). The display multiplex-
ing sequence is also reset, which can give rise to a
one-time display flicker when the register is written.
Global Clear Digit Data (R Data Bit D5) Format
When the R bit (Table 22) is set, the segment and
annunciator data are cleared.
Display Mode (M Data Bit D6) Format
The M bit (Table 23) selects the display modes (Table 1).
The display modes trade the maximum allowable num-
ber of digits (mode 96/2) against the availability of
annunciator segments (mode 48/1).
Blink Phase Readback (P Data Bit D7) Format
When the configuration register is read, the P bit
reflects the blink phase at that time (Table 24).
Serial Interface
Serial Addressing
The MAX6853 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX6853, and generates the SCL clock that
synchronizes the data transfer (Figure 6).
The MAX6853 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7k
,
is required on the SDA. The MAX6853 SCL line oper-
ates only as an input. A pullup resistor, typically 4.7k
,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 7) sent by a master, followed by the MAX6853
7-bit slave address plus R/W bit (Figure 10), a register
address byte, 1 or more data bytes, and finally a STOP
condition (Figure 7).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 7).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 8).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 9). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX6853, the
MAX6853 generates the acknowledge bit because the
MAX6853 is the recipient. When the MAX6853 is trans-
mitting to the master, the master generates the
acknowledge bit because the master is the recipient. In
this case, the master acknowledges all bytes received
from the MAX6853 except for the last byte required,
after which the master issues a STOP condition to signi-
fy end of transmission.
Slave Address
The MAX6853 has a 7-bit-long slave address (Figure
10). The eighth bit following the 7-bit slave address is
the R/W bit. Set it low for a write command and high for
a read command.
The first 5 bits (MSBs) of the MAX6853 slave address
are always 11101. Slave address bits A1 and A0 are
selected by the address input pins AD0. This input
may be connected to GND, V+, SDA, or SCL. The
MAX6853 has four possible slave addresses (Table 7)
and therefore a maximum of four MAX6853 devices
may share the same interface.
Message Format for Writing
A write to the MAX6853 comprises the transmission of
the MAX6853's slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte, which deter-
mines which register of the MAX6853 is to be written by
the next byte, if received. If a STOP condition is detect-
ed after the command byte is received, then the
MAX6853 takes no further action (Figure 11) beyond
storing the command byte.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX6853 selected by the command byte (Figure 12).
If multiple data bytes are transmitted before a STOP con-
dition is detected, these bytes are generally stored in
subsequent MAX6853 internal registers because the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX6854UK16D3 | Nanopower µP Supervisory Circuits with Manual Reset and Watchdog Timer |
| MAX6854UK16D3-T | Nanopower µP Supervisory Circuits with Manual Reset and Watchdog Timer |
| MAX6854UK23D3 | Nanopower µP Supervisory Circuits with Manual Reset and Watchdog Timer |
| MAX6854UK23D3-T | Nanopower µP Supervisory Circuits with Manual Reset and Watchdog Timer |
| MAX6854UK26D3 | Nanopower µP Supervisory Circuits with Manual Reset and Watchdog Timer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX6853AEE+T | 功能描述:VFD驅(qū)動(dòng)器 RoHS:否 制造商:Maxim Integrated 工作電源電壓:8 V to 76 V, 3 V to 5.5 V 電源電流:0.9 mA, 700 uA 最大工作溫度:+ 125 C 封裝 / 箱體:SOIC-20 封裝:Tube |
| MAX6853AEE-T | 功能描述:VFD驅(qū)動(dòng)器 RoHS:否 制造商:Maxim Integrated 工作電源電壓:8 V to 76 V, 3 V to 5.5 V 電源電流:0.9 mA, 700 uA 最大工作溫度:+ 125 C 封裝 / 箱體:SOIC-20 封裝:Tube |
| MAX6854UK16D1+T | 功能描述:監(jiān)控電路 Single nPower Supervisor RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6854UK16D1-T | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| MAX6854UK16D2+T | 功能描述:監(jiān)控電路 Single nPower Supervisor RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開(kāi)關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。