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參數資料
| 型號： | MAX6621AUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 13/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSLATOR PECI-I2C 10-MSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 邏輯功能： | 變換器 |
| 位數： | 1 |
| 輸入類型： | PECL |
| 輸出類型： | I²C? |
| 通道數： | 1 |
| 輸出/通道數目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -20°C ~ 120°C |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
MAX6621
PECI-to-I2C Translator
4
_______________________________________________________________________________________
Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design; not production tested.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VCC and 0.7 x VCC.
Note 5: ISINK
≤ 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x VCC and 0.7 x VCC.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 7: The MAX6621 must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the mini-
mum time less than 500μs. tBIT limits apply equally to tBIT-A and tBIT-M.
Note 8: The minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse.
Note 9: Extended trace lengths can appear as additional nodes.
Note 10: The client may deassert its low idle drive prior to the falling edge of the first bit of the message by using the rising edge to
detect a message start. However, the time delay must be sufficient to qualify the rising edge as a true message rather than
a noise spike.
Note 11: The message stop is defined by two consecutive periods when the bus has no rising edge. Tolerance around this time is
based on the tBIT-M error budget.
Note 12: tSETUP is not additive with tSTOP. Rather, these times may overlap.
TIMING CHARACTERISTICS (continued)
(
Typical Application Circuit, VCC = +3V to +3.6V, VREF = +0.95V to +1.26V, TA = -20°C to +120°C, unless otherwise noted. Typical
values are at VCC = +3.3V, VREF = +1.0V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bit Time Jitter
tBIT, jitter
Between adjacent bits in an PECI message
header or data bytes after timing has been
negotiated
1%
Change in Bit Time
tBIT, drift
Across a PECI address or PECI message
bits as driven by MAX6621
2%
High-Level Time for Logic-High
tH1
(Note 8)
0.6
0.75
0.8
x tBIT
High-Level Time for Logic-Low
tH0
0.2
0.3
0.4
x tBIT
Client Asserts PECI High
During Logic-High
tSU
0
0.2
x tBIT-M
Rise Time
tR
Measured from VOL to VPMAX,
VREF(nom) -5% (Note 9)
30 +
5/Node
ns
Fall Time
tF
Measured from VOH to VNMAX,
VREF(nom) +5% (Note 9)
30/Node
ns
Hold Time
tHOLD
Time for client to maintain a low idle drive
after MAX6621 begins a message (Note 10)
0.5
x tBIT-1
Stop Time
tSTOP
A constant low level driven by MAX6621
(Notes 8, 11)
2x tBIT-M
Maximum Dwell Time of the
PECI Client
tRESET
From the end of a ResetDevice command
to the next message to which the reset
client must be able to respond
0.4
ms
Minimum PECI Low Time
Preceding a Message
tSETUP
If the prior tBIT is not known by MAX6621,
the maximum tBIT must be assumed and
tSETUP = 1ms in this case (Note 12)
2x tBIT-X
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