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參數(shù)資料
| 型號(hào)： | MAX6618AUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PECI-TO-I2C TRANSLATOR 10UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 邏輯功能： | 變換器 |
| 位數(shù)： | 1 |
| 輸入類型： | PECL |
| 輸出類型： | I²C? |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -20°C ~ 120°C |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
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Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
MAX6618
PECI-to-I2C Translator
16
Maxim Integrated
configuring the MAX6618’s command byte by perform-
ing a write. The master can now read N consecutive
bytes from the MAX6618 with the first data byte being
read from the register addressed by the initialized com-
mand byte (Figure 10).
Packet Error Checksum (PEC)
All MAX6618 I2C packets have an optional packet error
checksum (PEC). The PEC is implemented in accor-
dance with the SMBus specification, versions 1.1 and
2. The MAX6618 accepts commands with or without
PEC. The PEC for device responses is optional and can
be disabled in the CONFIG0 register.
Applications Information
Operation with Multiple Masters
If the MAX6618 is operated on a 2-wire interface with
multiple masters, a master reading the MAX6618
should use a repeated START between the write that
sets the MAX6618’s address pointer, and the read(s)
that takes the data from the location(s) (Table 16). This
is because it is possible for master 2 to take over the
bus after master 1 has set up the MAX6618’s address
pointer, but before master 1 has read the data. If mas-
ter 2 subsequently changes the MAX6618’s address
pointer, master 1’s delayed read can be from an unex-
pected location. The use of multiple masters is not rec-
ommended.
I2C Address Range
In addition to the four MSBs (0101), the I2C slave
address includes bit A0 (set by the address input AD0)
and bits A2:A1 (set to 01). See Table 16.
Choosing Pullup Resistors
I2C requires pullup resistors to provide a logic-high level
to data and clock lines. There are tradeoffs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every device
connected to the bus introduces some capacitance even
when the device is not in operation. I2C specifies a mini-
mum 300ns rise time to go from low to high (30% to 70%)
for fast mode, which is defined for a date rate of 400kbps
(refer to the I2C specifications for details). To meet the
rise time requirement, choose pullup resistors so that the
rise time tR = 0.85RPULLUP x CBUS < 300ns. For typical
1
2
3
4
5
10
9
8
7
6
VREF
AD1
AD2
GND
SDA
AD0
AGND
PECI
MAX6618
MAX
+
TOP VIEW
VCC
SCL
Pin Configuration
A6:A1
(FIXED)
A0
(SET BY AD0 PIN)
I2C ADDRESS BYTE
INCLUDING R/W BIT
010101
0
54h, 55h
010101
1
56h, 57h
Table 16. MAX6618 Slave Addresses
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 μMAX
U10+2
Chip Information
PROCESS: CMOS
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