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參數(shù)資料
| 型號： | MAX6618AUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PECI-TO-I2C TRANSLATOR 10UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 邏輯功能： | 變換器 |
| 位數(shù)： | 1 |
| 輸入類型： | PECL |
| 輸出類型： | I²C? |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -20°C ~ 120°C |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
MAX6618
PECI-to-I2C Translator
14
Maxim Integrated
Data Transfer and Acknowledge
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 7).
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 8). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so that the SDA line is stable
low during the high period of the clock pulse. When the
master is transmitting to the MAX6618, the MAX6618
generates the acknowledge bit because the MAX6618
is the recipient. When the MAX6618 is transmitting to
the master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX6618 has a 7-bit long slave address (Figure 9).
The 8th bit following the 7-bit slave address is the R/W
bit. The R/W bit is low for a write command and high for
a read command.
The first four bits of the MAX6618 slave address (A6:A3)
are always 0101. Bits A2:A1 are set during the manufac-
turing process to 0:1. A0 is selected by the address
input AD0. AD0 can be connected to GND or VCC. The
MAX6618 has two possible slave addresses selectable
by AD0. Therefore, a maximum of two MAX6618 devices
can be controlled independently from the same interface
(see the
I2C Address Range section).
Message Format for Writing to the MAX6618
A write to the MAX6618 consists of the transmission of
the MAX6618’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The com-
mand byte determines which register of the MAX6618
is to be written to by the next byte or read from during
the next read transmission. If a STOP condition is
detected after the command byte is received, then the
MAX6618 takes no further action beyond setting the
register address.
The bytes received after the command byte are data
bytes. The data bytes go into the register of the
01
101
A0
ACK
0
SDA
SCL
Figure 9. Slave Address
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGEMENT
START
CONDITION
SDA BY
RECEIVER
12
89
S
Figure 8. Acknowledge
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