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參數(shù)資料
| 型號： | MAX6618AUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/17頁 |
| 文件大小： | 0K |
| 描述： | IC PECI-TO-I2C TRANSLATOR 10UMAX |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 邏輯功能： | 變換器 |
| 位數(shù)： | 1 |
| 輸入類型： | PECL |
| 輸出類型： | I²C? |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -20°C ~ 120°C |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
MAX6618
PECI-to-I2C Translator
3
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit, VCC = +3V to +3.6V, VREF = +0.95V to +1.26V, TA = -20°C to +120°C, unless otherwise noted. Typical
values are at VCC = +3.3V, VREF = +1.0V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Hysteresis
VH
0.1
x VREF
V
Low-Level Sinking Current
IIL
0.5
1.0
mA
High-Level Sourcing Current
IIH
-6
mA
Input Capacitance
CI
(Note 2)
10
pF
Signal-Noise Immunity Above
300MHz
VN
(Note 2)
0.1
x VREF
VP-P
TIMING CHARACTERISTICS
(
Typical Application Circuit, VCC = +3V to +3.6V, VREF = +0.95V to +1.26V, TA = -20°C to +120°C, unless otherwise noted. Typical
values are at VCC = +3.3V, VREF = +1.0V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2C INTERFACE
Serial-Clock Frequency
fSCL
400
kHz
Bus Free Time Between a
STOP and a START Condition
tBUF
1.3
s
Hold Time, (Repeated) START
Condition
tHD, STA
0.6
s
Repeated START Condition
Setup Time
tSU, STA
0.6
s
STOP Condition Setup Time
tSU, STO
0.6
s
Data Hold Time
tHD, DAT
(Note 3)
0.9
s
Data Setup Time
tSU, DAT
120
ns
SCL Clock-Low Period
tLOW
1.3
s
SCL Clock-High Period
tHIGH
0.6
s
Rise Time of Both SDA and
SCL Signals, Receiving
tR
(Notes 4, 5)
20
+ 0.1Cb
300
ns
Fall Time of Both SDA and
SCL Signals, Receiving
tF
(Notes 4, 5)
20
+ 0.1Cb
300
ns
Fall Time of SDA Transmitting
tF.TX
(Notes 4, 5)
20
+ 0.1Cb
250
ns
Pulse Width of Spike
Suppressed
tSP
(Notes 2, 6)
50
160
ns
Capacitive Load for Each
Bus Line
Cb
(Notes 2, 4)
400
pF
PECI INTERFACE
Overall time evident on PECI
0.495
500
Bit Time (Note 7)
tBIT
Driven by MAX6618
0.495
250
s
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