參數(shù)資料
型號(hào): MAX5965AEAX+
廠商: Maxim Integrated
文件頁(yè)數(shù): 23/54頁(yè)
文件大小: 1334K
描述: IC PSE CTRLR FOR POE 36SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類型: 以太網(wǎng)供電控制器(PoE)
應(yīng)用: IP 電話,LAN 網(wǎng)絡(luò)供電,網(wǎng)絡(luò)路由器和交換機(jī)
內(nèi)部開關(guān): 無(wú)
電源電壓: 2.4 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-BSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 36-SSOP
包裝: 管件
High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
______________________________________________________________________________________   23
Digital Logic
V
DD
supplies power for the internal logic circuitry. V
DD
ranges from +3.0V to +5.5V and determines the logic
thresholds for the CMOS connections (SDAIN, SDAOUT,
SCL, AUTO, SHD_, A_). This voltage range enables the
MAX5965A/MAX5965B to interface with a nonisolated
low-voltage microcontroller. The MAX5965A/MAX5965B
check the digital supply for compatibility with the internal
logic. The MAX5965A/MAX5965B also feature a V
DD
undervoltage lockout (V
DDUVLO
) of +2.0V. A V
DDUVLO
condition keeps the MAX5965A/MAX5965B in reset and
the ports shut off. Bit 0 in the supply event register shows
the status of V
DDUVLO
(Table 12) after V
DD
has recov-
ered. All logic inputs and outputs reference to DGND.
For AC-disconnected detection, DGND and AGND must
be connected together externally. Connect DGND to
AGND at a single point in the system as close as possi-
ble to the MAX5965A/MAX5965B.
Hardware Shutdown
SHD_ shuts down the respective ports without using the
serial interface. Hardware shutdown offers an emer-
gency turn-off feature that allows a fast disconnect of
the power supply from the port. Pull SHD_ low to
remove power. SHD_ also resets the corresponding
events and status register bits.
Interrupt
The MAX5965A/MAX5965B contain an open-drain logic
output (INT) that goes low when an interrupt condition
exists. R00h and R01h (Tables 6 and 7) contain the defin-
itions of the interrupt registers. The mask register R01h
determines events that trigger an interrupt. As a response
to an interrupt, the controller reads the status of the event
register to determine the cause of the interrupt and takes
subsequent actions. Each interrupt event register also
contains a Clear on Read (CoR) register. Reading
through the CoR register address clears the interrupt. INT
remains low when reading the interrupt through the read-
only addresses. For example, to clear a startup fault on
the port 4 read address 09h (see Table 11). Use the glob-
al pushbutton bit in register 1Ah (bit 7, Table 23) to clear
interrupts, or use a software or hardware reset.
Undervoltage and
Overvoltage Protection
The MAX5965A/MAX5965B contain several undervoltage
and overvoltage protection features. Table 12 in the
Register Map and Description section shows a detailed
list of the undervoltage and overvoltage protection fea-
tures. An internal V
EE
undervoltage lockout (V
EEUVLO
) cir-
cuit keeps the MOSFET off and the MAX5965A/
MAX5965B in reset until V
AGND
- V
EE
exceeds 29V for
more than 3ms. An internal V
EE
overvoltage (V
EE_OV
) cir-
cuit shuts down the ports when (V
AGND
- V
EE
) exceeds
60V. The digital supply also contains an undervoltage
lockout (V
DDUVLO
). The MAX5965A/MAX5965B also fea-
ture three other undervoltage and overvoltage interrupts:
V
EE
undervoltage interrupt (V
EE_UV
), V
DD
undervoltage
interrupt (V
DD_UV
), and V
DD
overvoltage interrupt
(V
DD_OV
). A fault latches into the supply events register
(Table 12), but the MAX5965A/MAX5965B does not shut
down the ports with V
EE_UV
, V
DD_UV
, or V
DD_OV
.
DC Disconnect Monitoring
Setting R13h[DCD_EN_] bits high enables DC load moni-
toring during a normal powered state. If V
RS
(the voltage
across R
S
) falls below the DC load disconnect threshold,
V
DCTH
, for more than t
DISC
, the device turns off power
and asserts the LD_DISC_ bit of the corresponding port.
AC Disconnect Monitoring Features
(MAX5965B)
The MAX5965B features AC load disconnect monitor-
ing. Connect an external sine wave to OSC. The oscilla-
tor requirements are:
1)  V
P-P
x Frequency = 200V
P-P
x Hz ?5%
2)  Positive peak voltage > +2.2V
3)  Frequency > 60Hz
A 100Hz ?0%, 2V
P-P
?%, with +1.3V offset (V
PEAK
=
+2.3V typical) is recommended.
The MAX5965B buffers and amplifiers three times the
external oscillator signal and sends the signal to DET_,
where the sine wave is AC-coupled to the output. The
MAX5965B senses the presence of the load by monitor-
ing the amplitude of the AC current returned to DET_
(see the Functional Diagram).
Setting R13h[ACD_EN_] bits high enable AC load dis-
connect monitoring during a normal powered state. If
the AC current peak at the DET_ input falls below I
ACTH
for more than t
DISC
, the device turns off power and
asserts the LD_DISC_ bit of the corresponding port.
I
ACTH
is programmable using R23h[2:0].
An internal comparator checks for a proper amplitude of
the oscillator input. If the positive peak of the input sinu-
soid falls below a safety value of 2V (typ), OSC_FAIL
sets and the port shuts down. Power cannot be applied
to the ports when ACD_EN_ is set high and OSC_FAIL
is set high. Leave OSC unconnected or connect it to
DGND when not using AC-disconnect detection.
Thermal Shutdown
If the MAX5965A/MAX5965B die temperature reaches
+150癈, an overtemperature fault generates and the
MAX5965A/MAX5965B shut down. The MOSFETs turn off.
The die temperature of the MAX5965A/MAX5965B must
cool down below +130癈 to remove the overtemperature
fault condition. After a thermal shutdown, the part is reset.
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