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參數(shù)資料
| 型號： | MAX5888EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 3.3V 500MSPS 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 11ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 130mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 500M |
MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
______________________________________________________________________________________
15
Grounding, Bypassing, and Power-Supply
Considerations
Grounding and power-supply decoupling can strongly
influence the performance of the MAX5888. Unwanted
digital crosstalk may couple through the input, refer-
ence, power supply, and ground connections, affecting
dynamic performance. Proper grounding and power-
supply decoupling guidelines for high-speed, high-fre-
quency applications should be closely followed. This
reduces EMI and internal crosstalk that can significant-
ly affect the dynamic performance of the MAX5888.
Use of a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. High-speed signals should run on lines directly
above the ground plane. Since the MAX5888 has sepa-
rate analog and digital ground buses (AGND,
CLKGND, and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two planes.
Digital signals should be run above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Digital signals should be kept as far
away from sensitive analog inputs, reference inputs
sense lines, common-mode input, and clock inputs as
practical. A symmetric design of clock input and ana-
log output lines is recommended to minimize 2nd-order
harmonic distortion components and optimize the
DAC’s dynamic performance. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5888 supports three separate power-supply
inputs for analog (AVDD), digital (DVDD), and clock
(VCLK) circuitry. Each AVDD, DVDD, and VCLK input
should at least be decoupled with a separate 0.1F
capacitor as close to the pin as possible and their
opposite ends with the shortest possible connection to
the corresponding ground plane (Figure 13). Try to
minimize the analog and digital load capacitances for
optimized operation. All three power-supply voltages
should also be decoupled at the point they enter the
PC board with tantalum or electrolytic capacitors.
Ferrite beads with additional decoupling capacitors
forming a pi network could also improve performance.
The analog and digital power-supply inputs AVDD,
VCLK, and DVDD of the MAX5888 allow a supply volt-
age range of 3.3V ±5%.
O
-30
-60
-70
-73
-75
-80
-90
0.2
0.4 0.6
1.2
1.8
6.0
IMD REQUIREMENT: < -70dBc
30kHz 100kHz
MEASUREMENT BANDWIDTH
TRANSMITTER
EDGE
INBAND
OUTBAND
WORST-CASE
NOISE LEVEL
AMPLITUDE
(dBc)
FREQUENCY OFFSET FROM CARRIER (MHz)
Figure 11. GSM/EDGE Tx Mask
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
26
30
28
34
32
36
38
4-TONE MULTITONE POWER RATIO PLOT
(fCLK = 300MHz, fCENTER = 31.9702MHz)
fOUT (MHz)
4-TONE
MTPR
(dBm)
fT2
fT3
fT4
fT1
AOUT = -12dB FS
BW = 12MHz
fT1 = 30.0659MHz
fT2 = 31.0181MHz
fT3 = 33.0688MHz
fT4 = 34.0209MHz
Figure 12. 4-Tone MTPR Test Results, fCENTER = 31.97MHz,
fCLK = 300MHz
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| MAX5889EGK-D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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