參數(shù)資料
型號: MAX5888EGK+TD
廠商: Maxim Integrated Products
文件頁數(shù): 2/18頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 3.3V 500MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時間: 11ns
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 130mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 500M
MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
10
______________________________________________________________________________________
operation IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5888.
Clock Inputs (CLKP, CLKN)
The MAX5888 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the lowest possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For sin-
gle-ended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1F capacitor.
The CLKP and CLKN pins are internally biased to 1.5V.
This allows the user to AC-couple clock sources directly
to the device without external resistors to define the DC
level. The input resistance of CLKP and CLKN is >5k
.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from an
LVDS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled ECL drive for
best performance.
Data Timing Relationship
Figure 5 shows the timing relationship between differ-
ential, digital LVDS data, clock, and output signals. The
MAX5888 features a 1.4ns hold, a -1ns setup, and a
1.8ns propagation delay time. There is a 3.5 clock-
cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
LVDS-Compatible Digital Inputs
(B0P–B15P, B0N–B15N)
The MAX5888 features LVDS receivers on the bus input
interface. These LVDS inputs (B0P/N through B15P/N)
allow for a low-differential voltage swing with low con-
stant power consumption across a large range of
0.1
F
1.2V
REFERENCE
10k
IREF
RSET
DACREF
FSADJ
REFIO
IREF = VREFIO/RSET
CURRENT-STEERING
DAC
AVDD
IOUTP
IOUTN
Figure 2. Reference Architecture, Internal Reference
Configuration
IOUT
IOUTN
IOUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD
Figure 3. Simplified Analog Output Structure
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
1:1
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
TO
DAC
CLKP
0.1
F
0.1
F
CLKN
CLKGND
25
25
Figure 4. Differential Clock Signal Generation
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