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參數(shù)資料
| 型號： | MAX5885EGM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 3.3V 200MSPS 48-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 135mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-QFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 200M |
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
______________________________________________________________________________________
15
harmonic distortion components and optimize the
DAC’s dynamic performance. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5885 supports three separate power-supply
inputs for analog (AVDD), digital (DVDD), and clock
(VCLK) circuitry. Each AVDD, DVDD, and VCLK input
should at least be decoupled with a separate 0.1F
capacitor as close to the pin as possible and their
opposite ends with the shortest possible connection to
the corresponding ground plane (Figure 12). All three
power-supply voltages should also be decoupled at the
point they enter the PC board with tantalum or elec-
trolytic capacitors. Ferrite beads with additional decou-
pling capacitors forming a pi network could also
improve performance.
The analog and digital power-supply inputs AVDD,
VCLK, and DVDD of the MAX5885 allow a supply volt-
age range of 3.3V ±5%.
The MAX5885 is packaged in a 48-pin QFN-EP
(package code: G4877-1), providing greater design
flexibility, increased thermal efficiency**, and optimized
AC performance of the DAC. The EP enables the user
to implement grounding techniques, which are neces-
sary to ensure highest performance operation. The EP
must be soldered down to AGND.
In this package, the data converter die is attached to an
EP lead frame with the back of this frame exposed at the
package bottom surface, facing the PC board side of the
package. This allows a solid attachment of the package
to the PC board with standard infrared (IR) flow soldering
techniques. A specially created land pattern on the PC
board, matching the size of the EP (5mm 5mm),
ensures the proper attachment and grounding of the
DAC. Designing vias*** into the land area and imple-
menting large ground planes in the PC board design
allow for highest performance operation of the DAC. An
array of at least 3 3 vias (
≤0.3mm diameter per via hole
and 1.2mm pitch between via holes) is recommended for
this 48-pin QFN-EP package.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every indi-
vidual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset point. For a DAC, the offset point is the
step value when the digital input is at midscale. This
error affects all codes by the same amount.
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
26
30
28
34
32
36
38
FOUR-TONE MULTITONE POWER RATIO PLOT
(fCLK = 150MHz, fCENTER = 31.9885MHz)
fOUT (MHz)
OUTPUT
POWER
(dBm)
AOUT = -12dB FS
fT1 fT2
fT3
fT4
fT1 = 29.9744MHz
fT2 = 30.9998MHz
fT3 = 32.9773MHz
fT4 = 33.8196MHz
Figure 11. 4-Tone MTPR Test Results
**Thermal efficiency is not the key factor, since the MAX5885 features low-power operation. The exposed pad is the key element to
ensure a solid ground connection between the DAC and the PC board’s analog ground layer.
***Vias connect the land pattern to internal or external copper planes. It is important to connect as many vias as possible to the analog
ground plane to minimize inductance.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MAX5885EVKIT | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Evaluation Kit for the MAX5883 MAX5884 MAX5885 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5886EGK | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX5886EGK+D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 500Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5886EGK+TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 500Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5886EGK-D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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