參數(shù)資料
型號: MAX5885EGM+TD
廠商: Maxim Integrated Products
文件頁數(shù): 16/18頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 3.3V 200MSPS 48-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設置時間: 11ns
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 135mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-QFN 裸露焊盤
供應商設備封裝: 48-QFN-EP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 200M
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________
7
Pin Description
PIN
NAME
FUNCTION
1
B1
Data Bit 1
2
B0
Data Bit 0 (LSB)
3XOR
XOR Input Pin.
XOR = 1 inverts the digital input data.
XOR = 0 leaves the digital input data unchanged.
XOR has an internal pulldown resistor and may be left unconnected if not used.
4, 9
VCLK
Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1F capacitor to the nearest CLKGND.
5, 8
CLKGND
Clock Ground
6
CLKP
Converter Clock Input. Positive input terminal for the converter clock.
7
CLKN
Complementary Converter Clock Input. Negative input terminal for the converter clock.
10
PD
Power-Down Input. PD pulled high enables the DAC’s power-down mode. PD pulled low allows for
normal operation of the DAC.
11, 21, 23
AVDD
Analog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1F capacitor to the nearest AGND.
12, 17, 20,
22, 24, EP
AGND
Analog Ground. Exposed paddle (EP) must be connected to AGND.
13
REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 0.1F
capacitor to AGND. Can be driven with an external reference source.
14
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale
output current, connect a 2k
resistor between FSADJ and DACREF.
15
DACREF
Return Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2k
resistor
between FSADJ and DACREF.
16, 25, 26,
27, 28, 29
N.C.
No connection. Do not connect to these pins. Do not tie these pins together.
18
IOUTN
Complementary DAC Output. Negative terminal for differential current output. The full-scale output
current range can be set from 2mA to 20mA.
19
IOUTP
DAC Output. Positive terminal for differential current output. The full-scale output current range can
be set from 2mA to 20mA.
30
SEL0
Mode Select Input SEL0. This pin has an internal pulldown resistor; it can be left open to disable the
segment-shuffling function (see the Segment Shuffling section).
31, 43
DVDD
Digital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1F capacitor to the nearest DGND.
32, 42
DGND
Digital Ground
33
B15
Data Bit 15 (MSB)
34
B14
Data Bit 14
35
B13
Data Bit 13
36
B12
Data Bit 12
37
B11
Data Bit 11
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