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參數(shù)資料
| 型號： | MAX5875EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DUAL 200MSPS 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 14ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 200M |
MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
14
______________________________________________________________________________________
For a single-ended unipolar output, select OUTIP
(OUTQP) as the output and ground OUTIN (OUTQN) to
GND. Driving the MAX5875 single-ended is not recom-
mended since additional noise and distortion will
be added.
The distortion performance of the DAC depends on the
load impedance. The MAX5875 is optimized for 50
differential double termination. It can be used with a
transformer output as shown in Figure 6 or just one 25
resistor from each output to ground and one 50
resis-
tor between the outputs (Figure 7). This produces a full-
scale output power of up to -2dBm, depending on the
output current setting. Higher termination impedance
can be used at the cost of degraded distortion perfor-
mance and increased output noise voltage.
Grounding, Bypassing, and Power-
Supply Considerations
Grounding and power-supply decoupling can strongly
influence the MAX5875 performance. Unwanted digital
crosstalk couples through the input, reference, power
supply, and ground connections, and affects dynamic
performance. High-speed, high-frequency applications
require closely followed proper grounding and power-
supply decoupling. These techniques reduce EMI and
internal crosstalk that can significantly affect the
MAX5875 dynamic performance.
Use a multilayer PCB with separate ground and power-
supply planes. Run high-speed signals on lines directly
above the ground plane. Keep digital signals as far
away from sensitive analog inputs and outputs, refer-
ence inputs sense lines, and clock inputs as practical.
Use a controlled-impedance symmetric design of clock
input and the analog output lines to minimize 2nd-order
harmonic-distortion components, thus optimizing the
DAC’s dynamic performance. Keep digital signal paths
short and run lengths matched to avoid propagation
delay and data skew mismatches.
The MAX5875 requires five separate power-supply inputs
for analog (AVDD1.8 and AVDD3.3), digital (DVDD1.8 and
DVDD3.3), and clock (AVCLK) circuitry. Decouple each
AVDD, DVDD, and AVCLK input pin with a separate 0.1F
capacitor as close to the device as possible with the
shortest possible connection to the ground plane (Figure
8). Minimize the analog and digital load capacitances for
optimized operation. Decouple all three power-supply
voltages at the point they enter the PCB with tantalum or
electrolytic capacitors. Ferrite beads with additional
decoupling capacitors forming a pi-network could also
improve performance.
The analog and digital power-supply inputs AVDD3.3,
AVCLK, and DVDD3.3 allow a 3.135V to 3.465V supply
voltage range. The analog and digital power-supply
inputs AVDD1.8 and DVDD1.8 allow a 1.71V to 1.89V
supply voltage range.
The MAX5875 is packaged in a 68-pin QFN-EP package,
providing greater design flexibility and optimized DAC
AC performance. The EP enables the use of necessary
grounding techniques to ensure highest performance
operation. Thermal efficiency is not the key factor, since
the MAX5875 features low-power operation. The exposed
pad ensures a solid ground connection between the DAC
and the PCB’s ground layer.
MAX5875
16
OUTIP/OUTQP
OUTIN/OUTQN
DATA15–DATA0
GND
25
50
25
OUTP
OUTN
Figure 7. Differential Output Configuration
MAX5875
16
OUTIP/OUTQP
OUTIN/OUTQN
DATA15–DATA0
0.1
F
AVDD1.8
DVDD1.8
0.1
F
0.1
F
0.1
F
AVDD3.3
DVDD3.3
0.1
F
AVCLK
BYPASSING—DAC LEVEL
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
Figure 8. Recommended Power-Supply Decoupling and
Bypassing Circuitry
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| MAX5876EGK+D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 2Ch 250Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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