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參數(shù)資料
| 型號(hào)： | MAX5875EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DUAL 200MSPS 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 14ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 200M |
MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
12
______________________________________________________________________________________
The MAX5875 includes a single-ended, CMOS-compati-
ble XOR input. Input data (all bits) are compared with the
bit applied to XOR through exclusive-OR gates. Pulling
XOR high inverts the input data. Pulling XOR low leaves
the input data noninverted. By applying a previously
encoded pseudo-random bit stream to the data input and
applying decoding to XOR, the digital input data can be
decorrelated from the DAC output, allowing for the trou-
bleshooting of possible spurious or harmonic distortion
degradation due to digital feedthrough on the printed cir-
cuit board (PCB).
A15/B15–A0/B0, XOR, and SELIQ are latched on the ris-
ing edge of the clock. In single-port mode (DORI pulled
low) a logic-high signal on SELIQ directs the B15–B0
data onto the I-DAC inputs. A logic-low signal at SELIQ
directs data to the Q-DAC inputs. In dual-port (parallel)
mode (DORI pulled high), data on pins A15–A0 are
directed onto the Q-DAC inputs and B15–B0 are directed
onto the I-DAC inputs.
Power-Down Operation (PD)
The MAX5875 also features an active-high power-
down mode that reduces the DAC’s digital current
tS
tH
tPD
DATA15–DATA0, XOR
CLK
DAC OUTPUT
N0 - 1
N
N0 + 1
N0 + 2
N0 - 5
N0 - 4
N0 - 3
N0 - 2
N0 - 6
SELIQ
CLK
DATAIN
I0
Q2
I2
Q1
I1
I3
Q3
Q0
tS
tH
I OUT
Q OUT
tPD
I0 - 5
I0 - 4
I0 - 2
I0 - 3
I0 - 6
Q0 - 6
Q0 - 5
Q0 - 4
Q0 - 3
Q0 - 2
(a) DUAL-PORT (PARALLEL) TIMING DIAGRAM
(b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM
Figure 4. Timing Relationships Between Clock and Input Data for (a) Dual-Port (Parallel) Mode and (b) Single-Port (Interleaved) Mode
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