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參數(shù)資料
| 型號： | MAX5580-MAX5585 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quadruple Low-Power Differential Line Receiver 20-LCCC -55 to 125 |
| 中文描述： | 緩沖，快速建立，四路，12/10/8位，電壓輸出DAC |
| 文件頁數(shù)： | 27/34頁 |
| 文件大?。?/td> | 1206K |
| 代理商： | MAX5580-MAX5585 |
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M
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
______________________________________________________________________________________
27
UPIO Configuration
Table 21 lists the possible configurations for UPIO1 and
UPIO2. UPIO1 and UPIO2 use the selected function
when configured by the UP3–UP0 configuration bits.
LDAC
LDAC
controls the loading of the DAC registers. When
LDAC
is high, the DAC registers are latched, and any
change in the input registers does not affect the con-
tents of the DAC registers or the DAC outputs. When
LDAC
is low, the DAC registers are transparent, and the
values stored in the input registers are fed directly to the
DAC registers, and the DAC outputs are updated.
Drive
LDAC
low to asynchronously load the DAC regis-
ters from their corresponding input registers (DACs that
are in shutdown remain shut down). The
LDAC
input
does not require any activity on
CS
, SCLK, or DIN to
take effect. If
LDAC
is brought low coincident with a ris-
ing edge of
CS
(which executes a serial command
modifying the value of either DAC input register), then
LDAC
must remain asserted for at least 120ns following
the
CS
rising edge. This requirement applies only for
serial commands that modify the value of the DAC input
registers. See Figures 5 and 6 for timing details.
Table 21. UPIO Configuration Register Bits (UP3–UP0)
UPIO CONFIGURATION BITS
UP3
UP2
UP1
UP0
FUNCTION
DESCRIPTION
0
0
0
0
LDAC
Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers
with data from input registers.
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
SET
MID
CLR
PDL
Active-Low Input. Drive low to set all input and DAC registers to full scale.
Active-Low Input. Drive low to set all input and DAC registers to midscale.
Active-Low Input. Drive low to set all input and DAC registers to zero scale.
Active-Low Power-Down Lockout Input. Drive low to disable software shutdown.
This mode is reserved. Do not use.
Reserved
0
1
1
0
SHDN1K
Active-Low 1k
Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5580/MAX5582/MAX5584, drive
SHDN1K
low to pull OUTA–OUTD to AGND
with 1k
. For the MAX5581/MAX5583/MAX5585, drive
SHDN1K
low to leave
OUTA–OUTD high impedance.
0
1
1
1
SHDN100K
Active-Low 100k
Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5580/MAX5582/MAX5584, drive
SHDN100K
low to pull OUTA–OUTD to
AGND with 100k
. For the MAX5581/MAX5583/MAX5585, drive low to leave
OUTA–OUTD high impedance.
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
DOUTRB
DOUTDC0
DOUTDC1
GPI
GPOL
GPOH
Data Read-Back Output
M od e 0 D ai sy- C hai n D ata O utp ut. D ata i s cl ocked out on the fal ng ed g e of S C LK.
Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK.
General-Purpose Logic Input
General-Purpose Logic-Low Output
General-Purpose Logic-High Output
1
1
1
0
TOGG
Toggle Input. Toggles DAC outputs between data in input registers and data in
DAC registers. Drive low to set all DAC outputs to values stored in input registers.
Drive high to set all DAC outputs to values stored in DAC registers.
1
1
1
1
FAST
Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3μs) mode or drive
high to select SLOW (6μs) settling mode. Overrides the SPDA–SPDD settings.
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