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參數(shù)資料
| 型號： | MAX5580-MAX5585 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quadruple Low-Power Differential Line Receiver 20-LCCC -55 to 125 |
| 中文描述： | 緩沖，快速建立，四路，12/10/8位，電壓輸出DAC |
| 文件頁數(shù)： | 25/34頁 |
| 文件大?。?/td> | 1206K |
| 代理商： | MAX5580-MAX5585 |
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M
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
______________________________________________________________________________________
25
Settling-Time-Mode Write Example:
To configure DACA and DACD into FAST mode and
DACB and DACC into SLOW mode, use the command
in Table 12.
To read back the settling-time-mode bits, use the com-
mand in Table 13.
CPOL and CPHA Control Bits
The CPOL and CPHA control bits of the
MAX5580–MAX5585 are defined the same as the CPOL
and CPHA bits in the SPI standard. Set the DAC’s
CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or
CPOL = 1 and CPHA = 1 for MICROWIRE and SPI
applications requiring the clocking of data in on the ris-
ing edge of SCLK. Set the DAC’s CPOL and CPHA bits
to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA =
0 for DSP and SPI applications, requiring the clocking
of data in on the falling edge of SCLK (refer to the
Programmer’s Handbook
and see Table 14 for details).
At power-up, if
DSP
= DV
DD
, the default value of CPHA
is zero and if
DSP
= DGND, the default value of CPHA
is one. The default value of CPOL is zero at power-up.
To write to the CPOL and CPHA bits, use the command
in Table 15.
To read back the device’s CPOL and CPHA bits, use
the command in Table 16.
Table 12. Settling-Time-Mode Write Example
DATA
DIN
CONTROL BITS
0
DATA BITS
X
1
1
1
1
1
0
X
X
X
X
1
0
0
1
X = Don’t care.
Table 13. Settling-Time-Mode Read Command
DATA
DIN
D OU TRB
CONTROL BITS
0
X
DATA BITS
X
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
X
X
X
X
X
X
X
X
X
X
S P D D S P D C S P D B S P D A
Table 16. CPOL and CPHA Read Command
DATA
DIN
D OU TRB
CONTROL BITS
1
X
DATA BITS
X
X
1
X
1
X
1
X
0
X
0
X
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
C P O L
C P H A
Table 14. CPOL and CPHA Bits
CPOL
CPHA
DESCRIPTION
0
0
Default values at power-up when
DSP
is connected to DV
DD
. Data is clocked in on the rising edge
of SCLK.
0
1
Default values at power-up when
DSP
is connected to DGND. Data is clocked in on the falling edge
of SCLK.
1
1
0
1
Data is clocked in on the falling edge of SCLK.
Data is clocked in on the rising edge of SCLK.
Table 15. CPOL and CPHA Write Command
DATA
DIN
CONTROL BITS
1
DATA BITS
X
1
1
1
0
0
0
0
X
X
X
X
X
C P O L C P H A
X = Don’t care.
X = Don’t care.
X = Don’t care.
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