參數資料
型號: MAX536
廠商: Maxim Integrated Products, Inc.
英文描述: Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface
中文描述: 校準型、四路、12位、電壓輸出DAC,串行接口
文件頁數: 7/24頁
文件大?。?/td> 361K
代理商: MAX536
MAX537_M
Note 2:
Guaranteed by design.
Note 3:
Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4:
Digital inputs at 2.4V; with digital inputs at CMOS levels, I
DD
decreases slightly.
Note 5:
All input signals are specified with t
R
= t
F
5ns. Logic input swing is 0V to 5V.
Note 6:
Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pull-up.)
Note 7:
Serial data clocked out of SDO on SCK’s rising edge.
Note 10:
When disabled, SDO is internally pulled high.
M
Calibrated, Quad, 12-Bit
Voltage-Output DACs with S erial Interfac e
_______________________________________________________________________________________
7
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
75
MAX
140
170
130
165
UNITS
CS
Fall to SDO Enable
t
DV
C
LOAD
= 50pF
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
MAX537_C/E
MAX537_M
ns
CS
Rise to SDO Disable
(Note 10)
t
TR
C
LOAD
= 50pF
70
ns
LDAC
Pulse Width High
t
LDAC
MAX537_C/E
MAX537_M
MAX537_C/E
50
70
100
125
ns
CS
Pulse Width High
t
CSW
ns
ELECTRICAL CHARACTERISTICS—MAX537 (continued)
(V
DD
= +5V, V
SS
= -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, R
L
= 5k
, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.)
SCK Rise to
CS
Fall Delay
t
CS0
Continuous SCK,
SCK edge ignored
35
40
35
40
ns
CS
Rise to SCK Rise
Hold Time
t
CS1
SCK edge ignored
ns
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