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參數(shù)資料
| 型號： | MAX536 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface |
| 中文描述： | 校準型、四路、12位、電壓輸出DAC，串行接口 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MAX536 |
__________Applic ations Information
Interfac ing to the M68HC11*
PORT D of the 68HC11 supports SPI. The four registers
used for SPI operation are the Serial Peripheral Control
Register, the Serial Peripheral Status Register, the Serial
Peripheral Data I/O Register, and PORT D’s Data Direction
Register. These registers have a default starting location of
$1000.
On reset, the PORT D register (memory location $1008) is
cleared and bits 5-0 are configured as general-purpose
inputs. Setting bit 6 (SPE) of the Serial Peripheral Control
Register (SPCR) configures PORT D for SPI as follows:
BIT
7
NAME
–
6
5
4
3
2
1
0
–
SS
SCK
MOSI MISO
TXD
RXD
Bits 6 and 7 are not used. Writes to these bits are ignored.
The PORT D Data Direction Register (DDRD) deter-
mines whether the port bits are inputs or outputs. Its
configuration is shown below:
Setting DDD_ = 0 configures the port bit as an input, while
setting DDD_ = 1 configures the port bit as an output. Writes
to bits 6 and 7 have no effect.
In SPI mode with MSTR = 1, when a PORT D bit is expected
to be an input (
SS
, MISO, RXD), the corresponding DDRD bit
(DDD_) is ignored. If the bit is expected to be an output
(SCK, MOSI, TXD), the corresponding DDRD bit must be
set for the bit to be an output.
Table 3. Serial Peripheral Status-Register Definitions
M
Calibrated, Quad, 12-Bit
Voltage-Output DACs with S erial Interfac e
18
______________________________________________________________________________________
NAME
SPIE
SPE
MSTR
CPOL
CPHA
SPR1/0
SPR1
0
0
1
1
SPR0
0
1
0
1
μP clock divided by 2
μP clock divided by 4
μP clock divided by 16
μP clock divided by 32
DEFINITION
When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary.
Master/Slave select option
Determines the clock phase.
SPI Clock-Rate Select
Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a general-
purpose I/O port.
Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to
determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral
Status Register’s SPIF bit or MODF bit is set.
Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the
clock idles low.
Table 2. Serial Peripheral Control-Register Definitions
DWOM
NAME
DEFINITION
SPIF
SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR.
WCOL
MODF
The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by read-
ing the SPSR and then accessing the SPDR.
The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the “master” controller
has its
SS
line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR.
*M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals.
BIT
7
NAME
–
6
5
4
3
2
1
0
–
DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
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