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參數(shù)資料
| 型號： | MAX3638ETM+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, QCC48 |
| 封裝： | 7 X 7 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, TQFN-48 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 2523K |
| 代理商： | MAX3638ETM+ |
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
MAX3638
13
Internal Reset
During power-on, a power-on reset (POR) signal is gen-
erated to synchronize all dividers. A reset signal is also
generated if any control pin is changed. Outputs within a
bank are phase aligned, but outputs bank-to-bank may
not be phase aligned.
Applications Information
Output Frequency Configuration
The MAX3638 output frequencies (fQA, fQB, fQC) are
functions of the reference frequency (fREF) and the pin-
programmable dividers (A, B, C, F, M). The relationships
can be expressed as:
REF
QA
f
F
f
M
A
=
×
(1)
REF
QB
f
F
f
M
B
=
×
(2)
REF
QC
f
F
f
M
C
=
×
(3)
The frequency ranges for the selected reference clocks
are 18MHz to 33.5MHz for the crystal oscillator input,
15MHz to 160MHz for the LVCMOS input, and 15MHz to
350MHz for the differential input. The available dividers
are given in Tables 3 to 6.
For a given reference frequency fREF, the input divider
M, the PLL feedback divider F, and VCO prescale divider
P must be configured so the VCO frequency (fVCO) falls
within the specified ranges. Invalid PLL configuration
leads to VCO frequencies beyond the specified ranges
and can result in loss of lock. An expression for the VCO
frequency along with the specified ranges is given by:
REF
VCO
f
F P
M
=
× ×
(4)
3830MHz ≤ fVCO ≤ 4025MHz (5)
The prescale divider P is set by DP as given in Table 7.
In addition, the reference clock frequency and input
divider M must also be selected so the PFD compare
frequency (fPFD) falls within the specified range of
15MHz to 42MHz. If applicable, the higher fPFD should
be selected for optimal jitter performance.
VCO
REF
PFD
f
M
P F
=
×
(6)
15MHz ≤ fPFD ≤ 42MHz (7)
Note that the reference clock frequency is not limited by
the fPFD range when the PLL is in bypass mode.
Example Frequency Configuration
The following is an example of how to find divider ratios
for a valid PLL configuration, given a requirement of
input and output frequencies.
1) Select input and output frequencies for system clock-
ing.
fREF = 25MHz
fQA = 125MHz
fQB = 100MHz
fQC = 66.67MHz
2) Find the input divider M for a valid PFD compare
frequency. Using Table 3 and equations (6) and (7),
it is determined that M = ÷1 is the only valid option.
3) Find the feedback divider F and prescale divider P for
a valid fVCO. Using Tables 4 and 7 along with equa-
tions (4) and (5), it is determined that F = ÷40 and
P = ÷4 results in fVCO = 4000MHz, which is within the
valid range of the VCO.
4) Find the output dividers A, B, C for the required output
frequencies. Using Tables 5 and 6 and equations (1),
(2), and (3), it is determined that A = ÷8 gives fQA =
125MHz, B = ÷10 gives fQB = 100MHz, and C = ÷15
gives fQC = 66.67MHz.
Table 11 provides input and output frequencies along
with valid divider ratios for a variety of applications.
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| MAX3638ETM+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3638ETM+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3638EVKIT+ | 功能描述:計時器和支持產(chǎn)品 Not Available From Mouser RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3639ETM+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3639ETM+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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