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參數(shù)資料
| 型號： | MAX3638ETM+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, QCC48 |
| 封裝： | 7 X 7 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, TQFN-48 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 2523K |
| 代理商： | MAX3638ETM+ |
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
MAX3638
11
output interface. A PLL bypass mode is also available for
system testing or clock distribution.
Crystal Oscillator
The on-chip crystal oscillator provides the low-frequency
reference clock for the PLL. This oscillator requires an
external crystal connected between XIN and XOUT.
See the Crystal Selection and Layout section for more
information. The XIN and XOUT pins can be left open if
not used.
LVCMOS Clock Input
An LVCMOS-compatible clock source can be connected
to CIN to serve as the PLL reference clock. The input is
internally biased to allow AC- or DC-coupling (see the
Applications Information section). It is designed to oper-
ate from 15MHz to 160MHz. No signal should be applied
to CIN if not used.
Differential Clock Input
A differential clock source can be connected to DIN
to serve as the PLL reference clock. This input oper-
ates from 15MHz to 350MHz and contains an internal
100ω differential termination. This input can accept
DC-coupled LVPECL signals, and is internally biased to
accept AC-coupled LVDS, CML, and LVPECL signals
(see the Applications Information section). No signal
should be applied to DIN if not used.
Phase-Locked Loop (PLL)
The PLL takes the signal from the crystal oscillator,
LVCMOS clock input, or differential clock input and
synthesizes a low-jitter, high-frequency clock. The PLL
contains a phase-frequency detector (PFD), a charge
pump (CP), and a low phase noise VCO with a wide
3.83GHz to 4.025GHz frequency range. The high-fre-
quency VCO output is divided by prescale divider P and
then is connected to the PFD input through a feedback
divider. The PFD compares the reference frequency to
the divided-down VCO output and generates a control
signal that keeps the VCO locked to the reference clock.
The high-frequency VCO/P output clock is sent to the
output dividers. To minimize noise-induced jitter, the
VCO supply (VCCA) is isolated from the core logic and
output buffer supplies.
Dividers and Muxes
The dividers and muxes are set with three-level control
inputs. Divider settings and routing information are given
in Tables 1 to 7. See Table 11 for example divider con-
figurations used in various applications.
Table 1. PLL Input
Table 2. PLL Bypass
IN_SEL
INPUT
0
Crystal Input. XO circuit is disabled when not selected.
1
Differential Input. No signal should be applied to DIN if not selected.
NC
LVCMOS Input. No signal should be applied to CIN if not selected.
PLL_BP
PLL OPERATION
0
PLL Enabled for Normal Operation. All outputs from the A, B, and C banks are derived from the VCO.
1
PLL Bypassed. Selected input passes directly to the outputs. The VCO is disabled to minimize power consump-
tion and intermodulation spurs. Used for system testing or clock distribution.
NC
The outputs from A-bank and B-bank are derived from the VCO, but the C-bank outputs are directly driven from
the input signal for purposes of daisy chaining.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MAX3638ETM+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3638ETM+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3638EVKIT+ | 功能描述:計時器和支持產(chǎn)品 Not Available From Mouser RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3639ETM+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3639ETM+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Programmable RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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