參數(shù)資料
型號(hào): MAX3637ETM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 800 MHz, OTHER CLOCK GENERATOR, QCC48
封裝: 7 X 7 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, TQFN-48
文件頁數(shù): 7/23頁
文件大?。?/td> 2745K
代理商: MAX3637ETM+
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
MAX3637
15
Power-Supply Filtering
The MAX3637 is a mixed analog/digital IC. The PLL
contains analog circuitry susceptible to random noise.
To take full advantage of on-board filtering and noise
attenuation, in addition to excellent on-chip power-sup-
ply rejection, this part provides a separate power-supply
pin, VCCA, for the VCO circuitry. Figure 3 illustrates the
recommended power-supply filter network for VCCA.
The purpose of this design technique is to ensure clean
input power supply to the VCO circuitry and to improve
the overall immunity to power-supply noise. This net-
work requires that the power supply is +3.3V ±5%.
Decoupling capacitors should be used on all other sup-
ply pins for best performance. All supply connections
should be driven from the same source.
Ground Connection
The 48-pin TQFN package features an exposed pad
(EP), which provides a low resistance thermal path for
heat removal from the IC and also the electrical ground.
For proper operation, the EP must be connected to the
circuit board ground plane with multiple vias.
Crystal Selection and Layout
The MAX3637 features an integrated on-chip crystal
oscillator to minimize system implementation cost. The
crystal oscillator is designed to drive a fundamental
mode, AT-cut crystal resonator. See Table 12 for recom-
mended crystal specifications. See Figure 4 for the crys-
tal equivalent circuit and Figure 5 for the recommended
external capacitor connections. The crystal, trace, and
two external capacitors should be placed on the board
as close as possible to the XIN and XOUT pins to reduce
crosstalk of active signals into the oscillator. The total
load capacitance for the crystal is a combination of
external and on-chip capacitance. The layout shown
in Figure 6 gives approximately 1.7pF of trace plus
footprint capacitance per side of the crystal. Note the
ground plane is removed under the crystal to minimize
capacitance. There is approximately 2.5pF of on-chip
capacitance between XIN and XOUT. With an external
27pF capacitor connected to XIN and a 33pF external
capacitor connected to XOUT, the total load capacitance
for the crystal is approximately 18pF. The XIN and XOUT
pins can be left open if not used.
Figure 3. Power-Supply Filter
Table 12. Crystal Selection Parameters
Figure 4. Crystal Equivalent Circuit
Figure 5. Crystal, Capacitor Connections
VCC
VCCA
10.5
+3.3V ±5%
0.1F
10F
0.1F
MAX3637
XTAL
C0
CS
RS
LS
XIN
XOUT
27pF
CRYSTAL
(CL = 18pF)
33pF
MAX3637
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Crystal Oscillation Frequency
fOSC
18
25
33.5
MHz
Shunt Capacitance
C0
2.0
7.0
pF
Load Capacitance
CL
18
pF
Equivalent Series Resistance (ESR)
RS
10
50
I
Maximum Crystal Drive Level
200
F
W
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