參數(shù)資料
型號(hào): MAX3637ETM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 800 MHz, OTHER CLOCK GENERATOR, QCC48
封裝: 7 X 7 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, TQFN-48
文件頁(yè)數(shù): 4/23頁(yè)
文件大?。?/td> 2745K
代理商: MAX3637ETM+
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
MAX3637
12
LVDS/LVPECL Clock Outputs
The differential clock outputs (QA[4:0], QB[2:0], QC)
operate up to 800MHz and have a pin-programmable
LVDS/LVPECL output interface. See Tables 8 to 10.
When configured as LVDS, the buffers are designed
to drive transmission lines with a 100ω differential ter-
mination. When configured as LVPECL, the buffers are
designed to drive transmission lines terminated with 50ω
to VCC - 2V. Unused output banks can be disabled to
high impedance and unused outputs can be left open.
LVCMOS Clock Output
The LVCMOS clock output operates up to 160MHz and is
designed to drive a single-ended high-impedance load.
If unused, this output can be left open or the C-bank can
be disabled to high impedance.
Table 3. Input Divider M
Table 5. Output Divider A, B
Table 6. Output Divider C
Table 8. A-Bank Output Interface
Table 9. B-Bank Output Interface
Table 10. C-Bank Output Interface
Table 4. PLL Feedback Divider F
Table 7. Prescale Divider P
Note: When the on-chip XO is selected (IN_SEL = 0), the set-
ting DM = 0 is required.
QC_CTRL
QC AND QCC OUTPUT
0
QC = LVDS, QCC = LVCMOS
1
QC = LVPECL, QCC = LVCMOS
NC
QC and QCC disabled to high impedance
DF1
DF0
F DIVIDER RATIO
0
÷25
0
1
÷20
1
0
÷16
1
÷32
1
NC
÷24
NC
1
÷30
0
NC
÷40
NC
0
÷48
NC
÷28
DA1/DB1
DA0/DB0
A, B DIVIDER RATIO
0
÷2
0
1
÷3
1
0
÷4
1
÷5
1
NC
÷6
NC
1
÷8
0
NC
÷10
NC
0
÷12
NC
÷1
DC1
DC0
C DIVIDER RATIO
0
÷2
0
1
÷3
1
0
÷4
1
÷5
1
NC
÷6
NC
1
÷8
0
NC
÷10
NC
0
÷12
NC
÷25
DM
M DIVIDER RATIO
0
÷1
1
÷5
NC
÷4
DP
P DIVIDER RATIO
0
÷5
1
÷6
NC
÷8
QA_CTRL1
QA[2:0] OUTPUT
0
QA[2:0] = LVDS
1
QA[2:0] = LVPECL
NC
QA[2:0] disabled to high impedance
QA_CTRL2
QA[4:3] OUTPUT
0
QA[4:3] = LVDS
1
QA[4:3] = LVPECL
NC
QA[4:3] disabled to high impedance
QB_CTRL
QB[2:0] OUTPUT
0
QB[2:0] = LVDS
1
QB[2:0] = LVPECL
NC
QB[2:0] disabled to high impedance
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