參數(shù)資料
型號: MAX3637ETM+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 800 MHz, OTHER CLOCK GENERATOR, QCC48
封裝: 7 X 7 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, TQFN-48
文件頁數(shù): 11/23頁
文件大?。?/td> 2745K
代理商: MAX3637ETM+
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
MAX3637
19
Interfacing with LVDS Outputs
The equivalent LVDS output circuit is given in Figure 13.
These outputs provide 100ω differential output imped-
ance designed to drive a 100ω differential transmission
line terminated with a 100ω differential load. Example
interface circuits are shown in Figure 14. For more infor-
mation on LVDS terminations and how to interface with
other logic families, refer to Application Note 291: HFAN-
01.0: Introduction to LVDS, PECL, and CML.
Interfacing with LVCMOS Output
The equivalent LVCMOS output circuit is given in Figure
15. This output provides 15ω output impedance and
is designed to drive a high-impedance load. A series
resistor of 33ω is recommended at the LVCMOS output
before the transmission line. An example interface circuit
is shown in Figure 16.
Figure 13. Equivalent LVDS Output Circuit
Figure 14. Interface to LVDS Outputs
Figure 15. Equivalent LVCMOS Output Circuit
Figure 16. Interface to LVCMOS Output
ESD
STRUCTURES
Q_ _
VREG
VCC_ _
Q_ _
50
Z = 50
Q_ _
DC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT
Q_ _
MAX3637
LVDS*
+3.3V
LVDS
+3.3V
Z = 50
Q_ _
AC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT
*100 DIFFERENTIAL INPUT IMPEDANCE ASSUMED.
Q_ _
MAX3637
LVDS*
VDD
LVDS
+3.3V
0.1F
10
ESD
STRUCTURES
QCC
VCCQCC
QCC
33
Z = 50
HIGH
IMPEDANCE
MAX3637
LVCMOS
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