- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗11564 > MAX3421EETJ+T (Maxim Integrated Products)IC USB PERIPH/HOST CNTRL 32TQFN PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MAX3421EETJ+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 7/28闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC USB PERIPH/HOST CNTRL 32TQFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 鎺у埗鍣ㄩ鍨嬶細 | USB 澶栬ō(sh猫)鎺у埗鍣� |
| 鎺ュ彛锛� | USB/涓茶 |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V |
| 闆绘祦 - 闆绘簮锛� | 15mA |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 32-WFQFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 32-TQFN-EP锛�5x5锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 閰嶇敤锛� | MAX3421EVKIT-1+-ND - EVAL KIT FOR MAX3421E |
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MAX3421E
USB Peripheral/Host Controller
with SPI Interface
15
Maxim Integrated
Typical Operating Characteristics
(VCC = +3.3V, VL = +3.3V, TA = +25掳C.)
Detailed Description
The MAX3421E contains digital logic and analog cir-
cuitry necessary to implement a full-speed USB periph-
eral or a full-/low-speed host compliant to USB
specification rev 2.0. The MAX3421E is selected to
operate as either a host or peripheral by writing to the
HOST bit in the MODE (R27) register. The MAX3421E
features an internal USB transceiver with 卤15kV ESD
protection on D+, D-, and VBCOMP. A switchable
1.5k
惟 pullup resistor is provided on D+ and switchable
15k
惟 pulldown resistors are provided on both D+ and
D-. Any SPI master can communicate with the
MAX3421E through the SPI slave interface that oper-
ates in SPI mode (0,0) or (1,1). An SPI master accesses
the MAX3421E by reading and writing to internal regis-
ters. A typical data transfer consists of writing a first
byte that sets a register address and direction with
additional bytes reading or writing data to the register
or internal FIFO.
In peripheral mode, the MAX3421E contains 384 bytes
of endpoint buffer memory, implementing the following
endpoints:
EP0: 64-byte bidirectional CONTROL endpoint
EP1: 2 x 64-byte double-buffered BULK/INT
OUT endpoint
EP2: 2 x 64-byte double-buffered BULK/INT IN
endpoint
EP3: 64-byte BULK/INT IN endpoint
The choice to use EP1, EP2, EP3 as BULK or INTER-
RUPT endpoints is strictly a function of the endpoint
descriptors that the SPI master returns to the USB host
during enumeration.
In host mode, the MAX3421E contains 256 bytes of
send and receive FIFO memory:
SNDFIFO: Send FIFO鈥攄ouble-buffered 64-byte
FIFO
RCVFIFO: Receive FIFO鈥攄ouble-buffered 64-byte
FIFO
The host FIFOs can send SETUP, BULK, INTERRUPT,
and ISOCHRONOUS requests to a peripheral device, at
full speed or low speed. The MAX3421E accommodates
low-speed devices whether they are directly connected,
or connected through a USB hub. Because the
MAX3421E does much of the host housekeeping, it is
easy to program. The SPI master does a typical host
operation by setting the device address and endpoint,
launching a packet, and waiting for a completion inter-
rupt. Then it examines transfer result bits to determine
how the peripheral responded. It automatically gener-
ates frame markers (full-speed SOF packets or low-
speed keep-alive pulses), and ensures that packets are
dispatched at the correct times relative to these markers.
The MAX3421E register set and SPI interface is optimized
to reduce SPI traffic. An interrupt output pin, INT, notifies
the SPI master when USB service is required; for exam-
ple, when a packet arrives, a packet is sent, or the host
suspends or resumes bus activity. Double-buffered FIFOs
EYE DIAGRAM
MAX3421E
toc01
4
1
0
-1
0
1020304050607080
2
3
TIME (ns)
D+
AND
D-
(V)
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX3421EVKIT-1+ | 鍔熻兘鎻忚堪:鐣岄潰闁�(k膩i)鐧�(f膩)宸ュ叿 MAX3421E/20E Eval Kit RoHS:鍚� 鍒堕€犲晢:Bourns 鐢�(ch菐n)鍝�:Evaluation Boards 椤炲瀷:RS-485 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:ADM3485E 鎺ュ彛椤炲瀷:RS-485 宸ヤ綔闆绘簮闆诲:3.3 V |
| MAX3430CPA | 鍔熻兘鎻忚堪:RS-485鎺ュ彛IC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏁�(sh霉)鎿�(j霉)閫熺巼:250 Kbps 宸ヤ綔闆绘簮闆诲:3.3 V 闆绘簮闆绘祦:750 uA 宸ヤ綔婧害鑼冨湇:- 40 C to + 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
| MAX3430CPA+ | 鍔熻兘鎻忚堪:RS-485鎺ュ彛IC Fail-Safe 1/4-Unit 3.3V Transceiver RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏁�(sh霉)鎿�(j霉)閫熺巼:250 Kbps 宸ヤ綔闆绘簮闆诲:3.3 V 闆绘簮闆绘祦:750 uA 宸ヤ綔婧害鑼冨湇:- 40 C to + 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
| MAX3430CSA | 鍔熻兘鎻忚堪:RS-485鎺ュ彛IC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏁�(sh霉)鎿�(j霉)閫熺巼:250 Kbps 宸ヤ綔闆绘簮闆诲:3.3 V 闆绘簮闆绘祦:750 uA 宸ヤ綔婧害鑼冨湇:- 40 C to + 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
| MAX3430CSA+ | 鍔熻兘鎻忚堪:RS-485鎺ュ彛IC Fail-Safe 1/4-Unit 3.3V Transceiver RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏁�(sh霉)鎿�(j霉)閫熺巼:250 Kbps 宸ヤ綔闆绘簮闆诲:3.3 V 闆绘簮闆绘祦:750 uA 宸ヤ綔婧害鑼冨湇:- 40 C to + 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
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