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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MAX3421EETJ+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/28闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC USB PERIPH/HOST CNTRL 32TQFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 鎺у埗鍣ㄩ鍨嬶細 | USB 澶栬ō(sh猫)鎺у埗鍣� |
| 鎺ュ彛锛� | USB/涓茶 |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V |
| 闆绘祦 - 闆绘簮锛� | 15mA |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 32-WFQFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 32-TQFN-EP锛�5x5锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 閰嶇敤锛� | MAX3421EVKIT-1+-ND - EVAL KIT FOR MAX3421E |
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MAX3421E
USB Peripheral/Host Controller
with SPI Interface
13
Maxim Integrated
Note 3: Parameters are 100% production tested at TA = +25掳C. Specifications over temperature are guaranteed by design.
Note 4: Guaranteed by bench testing. Limits are not production tested.
Note 5: At VL = 1.4V to 2.5V, derate all the SPI timing characteristics by 50%. Not production tested.
Note 6: The minimum period is derived from SPI timing parameters.
Note 7: Time-to-exit suspend is dependent on the crystal used.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
USB TRANSMITTER TIMING CHARACTERISTICS (FULL-SPEED MODE)
D+, D- Rise Time
tRISE
CL = 50pF, Figures 8 and 9
4
20
ns
D+, D- Fall Time
tFALL
CL = 50pF, Figures 8 and 9
4
20
ns
Rise-/Fall-Time Matching
CL = 50pF, Figures 8 and 9 (Note 4)
90
110
%
Output-Signal Crossover Voltage
CL = 50pF, Figures 8 and 9 (Note 4)
1.3
2.0
V
USB TRANSMITTER TIMING CHARACTERISTICS (HOST LOW-SPEED MODE)
D+, D- Rise Time
tRISE
200pF
鈮� CL 鈮� 600pF, Figures 8 and 9
75
300
ns
D+, D- Fall Time
tFALL
200pF
鈮� CL 鈮� 600pF, Figures 8 and 9
75
300
ns
Rise-/Fall-Time Matching
200pF
鈮� CL 鈮� 600pF, Figures 8 and 9
80
120
%
Output-Signal Crossover Voltage
200pF
鈮� CL 鈮� 600pF, Figures 8 and 9
1.3
2.0
V
SPI BUS TIMING CHARACTERISTICS (VL = 2.5V) (Figures 10 and 11) (Note 5)
VL > 2.5V
38.4
Serial Clock (SCLK) Period (Note 6)
tCP
VL = 1.4V
77.7
ns
SCLK Pulse-Width High
tCH
17
ns
SCLK Pulse-Width Low
tCL
17
ns
SS Fall to MISO Valid
tCSS
20
ns
SS Leading Time Before the First
SCLK Edge
tL
30
ns
SS Trailing Time After the Last
SCLK Edge
tT
30
ns
Data-In Setup Time
tDS
5ns
Data-In Hold Time
tDH
10
ns
SS Pulse High
tCSW
200
ns
SCLK Fall to MISO Propagation
Delay
tDO
14.2
ns
SCLK Fall to MOSI Propagation
Delay
tDI
14.2
ns
SCLK Fall to MOSI Drive
tON
3.5
ns
SS High to MOSI High
Impedance
tOFF
20
ns
SUSPEND TIMING CHARACTERISTICS
Time-to-Enter Suspend
PWRDOWN = 1 to oscillator stop
5
s
Time-to-Exit Suspend
PWRDOWN = 1 to 0 to OSCOKIRQ (Note 7)
3
ms
TIMING CHARACTERISTICS
(
VCC = +3V to +3.6V, VL = +1.4V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V, VL =
+2.5V, TA = +25
掳C.) (Note 3)
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| MAX3430CPA+ | 鍔熻兘鎻忚堪:RS-485鎺ュ彛IC Fail-Safe 1/4-Unit 3.3V Transceiver RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏁�(sh霉)鎿�(j霉)閫熺巼:250 Kbps 宸ヤ綔闆绘簮闆诲:3.3 V 闆绘簮闆绘祦:750 uA 宸ヤ綔婧害鑼冨湇:- 40 C to + 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
| MAX3430CSA | 鍔熻兘鎻忚堪:RS-485鎺ュ彛IC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏁�(sh霉)鎿�(j霉)閫熺巼:250 Kbps 宸ヤ綔闆绘簮闆诲:3.3 V 闆绘簮闆绘祦:750 uA 宸ヤ綔婧害鑼冨湇:- 40 C to + 125 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
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