參數資料
型號: MAX1459AAP+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調理
英文描述: 2-Wire, 4-20mA Smart Signal Conditioner
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: 5.30 MM, 0.65 MM PITCH, SSOP-20
文件頁數: 23/24頁
文件大?。?/td> 243K
代理商: MAX1459AAP+T
MAX1459
Output Buffer
The output buffer (OUT) can swing within 50mV of the
supply rails with no load, or within 0.25V of either rail
while driving a 10k
load. OUT can easily drive 0.1F
of capacitance. The output is current limited and can
be shorted to either VDD or VSS indefinitely. If CS is
brought low, OUT goes high impedance, resulting in
typical output impedance of 1M
. This feature allows
parallel MAX1459 connections, reducing test system
wire harness complexity.
Bridge Drive
Fine FSO correction is accomplished by varying the
sensor excitation current with the 12-bit FSO DAC
(Figure 2). Sensor bridge excitation is performed by a
programmable current source capable of delivering up
to 2mA. The reference current at ISRC is established by
resistor RISRC and by the voltage at node ISRC (con-
trolled by the FSO DAC). The reference current flowing
through this pin is multiplied by a current mirror (AA
12) and then made available at BDRIVE for sensor exci-
tation. Modulation of this current with respect to tem-
perature can be used to correct FSOTC errors, while
modulation with respect to the output voltage (VOUT)
can be used to correct FSO linearity errors.
Voltage Drive Sensor
For sensors with negligible FSOTC, the MAX1459 can
be configured as a fixed-voltage drive by shorting ISRC
and BDRIVE. Offset TC can then be compensated with
RTEMP. Set configuration register bit 5 to 1, and con-
nect TEMPIN to a temperature-dependent voltage
source. This source can easily be generated by induc-
ing a current through RTEMP. For more information on
this application, refer to the MAX1459 Reference Man-
ual.
Digital-to-Analog Converters
The four 12-bit, sigma-delta DACs typically settle in
less than 100ms. The four DACs have a corresponding
memory register in EEPROM for storage of correction
coefficients.
The FSO DAC takes its reference from VDD and con-
trols VISRC, which sets the baseline sensor excitation
current. The FSO DAC is used for fine adjustments to
the FSO. The offset DAC also takes its reference from
VDD and provides a 1.22mV resolution with a VDD of
5V. The output of the offset DAC is fed into the output
summing junction where it is gained by approximately
2.3, which increases the resulting output-referred off-
set-correction resolution to 2.8mV.
Both the offset TC and FSOTC DACs take their refer-
ences from a temperature-dependent voltage. In
default mode, this voltage is internally connected to
BDRIVE. Alternatively, a different temperature sensor
can be used through TEMPIN by setting bit 5 of the
configuration register. This temperature sensor can be
either RTEMP or an external temperature resistor.
2-Wire, 4–20mA
Smart Signal Conditioner
8
_______________________________________________________________________________________
2.070
230
1
7
1.827
203
0
1
6
1.584
176
1
0
1
5
1.341
149
0
1
4
1.098
122
1
0
3
0.855
95
0
1
0
2
0.612
68
1
0
1
0.369
OUTPUT-
REFERRED IRO
DAC STEP SIZE
(VDD = 5V) (V)
41
PGA
GAIN
(+V/+V)
0
PGA
VALUE
A0
A2
0
A1
Table 2. PGA Gain Settings and IRO DAC
Step Size
0
-63
-1.25
1
0
-7
-54
-1.08
0
1
0
-6
-45
-0.90
1
0
1
0
-5
-36
-0.72
0
1
0
-4
-27
-0.54
1
0
-3
-18
-0.36
0
1
0
-2
-9
-0.18
1
0
-1
0
-0
+9
+0.18
1
0
1
+1
+18
+0.36
0
1
0
1
+2
+27
+0.54
1
0
1
+3
+36
+0.72
0
1
+4
+45
+0.90
1
0
1
+5
+54
+1.08
0
1
+6
VALUE
C0
C2
C1
SIGN
+63
OFFSET
CORREC-
TION AT
VDD = 5V
(mV)
+1.25
OFFSET
CORREC-
TION
PERCENT
OF VDD
(%)
1
IRO DAC
1
+7
Table 1. Input-Referred Offset DAC
Correction Values
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