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參數(shù)資料
| 型號： | MAX1459AAP+T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 2-Wire, 4-20mA Smart Signal Conditioner |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | 5.30 MM, 0.65 MM PITCH, SSOP-20 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 243K |
| 代理商： | MAX1459AAP+T |
MAX1459
2-Wire, 4–20mA
Smart Signal Conditioner
18
______________________________________________________________________________________
where OTC is the sensor offset TC error as a ppm/°C of
OUTFSO (Table 8),
T is the operating temperature
range in °C, and OFFTC COEF is the numerical decimal
value to be loaded into the DAC. For positive values,
set the OFFTC sign bit high; for negative values, set the
OFFTC sign bit low. If the absolute value of the OFFTC
COEF is larger than 4096, the sensor has a very large
offset TC error, which the MAX1459 is unable to com-
pletely correct without the use of a temperature sensor.
FSO Calibration
Perform FSO calibration at room temperature with a full-
scale sensor excitation:
1) Set FSOTC COEF to 1000.
2) At T1, adjust FSO DAC until VBDRIVE is about 2.5V.
3) Adjust offset DAC (and OFFSET sign bit, if needed)
until the T1 offset voltage is 0.5V (see OFFSET
Calibration section).
4) Measure the full-span output (measuredVFSO).
5) Calculate the ideal bridge voltage, VBIDEAL(T1),
using the following equation:
Note: If VBIDEAL(T1) is outside the allowable bridge
voltage swing of (VSS + 1.3V) to (VDD - 1.3V), readjust
the PGA gain setting. If VBIDEAL(T1) is too low,
decrease the PGA gain setting by one step and return
to step 2. If VBIDEAL(T1) is too high, increase the PGA
gain setting by one step and return to step 2.
6) Set VBIDEAL(T1) by adjusting the FSO DAC.
7) Readjust Offset DAC until the VOUT = 0.5V (see
OFFSET Calibration section).
Three-Step FSOTC Compensation
Step 1
Use the following procedure to determine FSOTC
COEF; four variables, A–D, will be used:
1) Name the existing FSO DAC coefficient A.
2) Change FSOTC DAC to 3000.
3) Adjust FSO DAC until VBDRIVE (T1) is equal to
VBIDEAL(T1).
4) Name the new FSO DAC coefficient B.
5) Readjust the offset voltage (by adjusting the Offset
DAC), if required, to VOUT = 0.5V.
At this point, it is important that no other changes be
made to the offset or offset TC DACs until the Offset TC
compensation step has been completed.
Step 2
To complete linear FSOTC compensation, take data
measurements at a second temperature, T2. The follow-
ing equation and procedure are suitable for any two
arbitrary temperatures where T2 > T1. The following
steps are performed at temperature T2:
1) Measure the full-span output (measuredVFSO(T2)).
2) Calculate VBIDEAL(T2) using the following equation:
3) Set VBIDEAL(T2) by adjusting the FSO DAC.
4) Name the current FSO DAC coefficient D.
5) Change FSOTC DAC to 1000.
6) Adjust FSO DAC until VBDRIVE is equal to
VBIDEAL(T2).
7) Name the FSO DAC coefficient C.
Step 3
into the following equation to compute FSOTC COEF:
1) Load this FSOTC COEF value into the FSOTC DAC.
2) Adjust the FSO DAC until VBDRIVE(T2) is equal to
VBIDEAL(T2).
This completes both FSO calibration and FSO TC com-
pensation.
Offset TC Compensation
The offset voltage at T1 was previously set to 0.5V;
therefore, any variation from this voltage at T2 is an
offset TC error. Perform the following steps:
1) Measure the offset voltage at T2.
2) Use the following equation to compute the correc-
tion required:
FSOTC COEF
1000 B - D
3000 C - A
B- D
C - A
=
() +
()
() + ()
VT2
V
1
desiredV
- measuredV
T2
measuredV
T2
BIDEAL
BDRIVE
FSO
() =
+
()
x
VT
V
1
desiredV
- measuredV
T
measuredV
T
BIDEAL
BDRIVE
FSO
1
() =
+
()
x
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