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參數(shù)資料
| 型號： | MAX1457AWI+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 0.1% Accurate Signal Conditioner for Piezoresistive Sensor Compensation |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 93K |
| 代理商： | MAX1457AWI+ |
MAX1457
0.1%-Accurate Signal Conditioner
for Piezoresistive Sensor Compensation
_______________________________________________________________________________________
5
_______________Detailed Description
The MAX1457 provides an analog amplification path for
the sensor signal and a digital path for calibration and
temperature correction. Calibration and correction are
achieved by varying the offset and gain of a program-
mable-gain amplifier (PGA) and by varying the sensor
bridge current. The PGA utilizes a switched-capacitor
CMOS technology, with an input-referred offset trim-
ming range of ±100mV (20mV/V) and an approximate
3V (input referred, at minimum gain of 54V/V) resolu-
tion (16 bits). The PGA provides eight gain values from
54V/V to 306V/V. The bridge current source is program-
mable from 0.1mA to 2mA, with a 15nA step size.
The MAX1457 uses five 16-bit DACs with calibration
coefficients stored in a low-cost external EEPROM. This
memory (an external 4096-bit EEPROM) contains the
following calibration coefficients as 16-bit words:
FSO (full-span output)
FSO TC (including nonlinearities)
Offset
Offset TC (including nonlinearities)
Pressure nonlinearity
Figure 1 shows a typical pressure-sensor output and
defines the offset, full-scale, and full-span output values
as a function of voltage.
Offset Correction
Initial offset calibration is accomplished by reading a
16-bit word (coefficient) from the EEPROM and writing it
to the OFFSET DAC. The resulting voltage (OFSTDAC)
is fed into a summing junction at the PGA output for
compensating the sensor offset with a resolution of
±0.2mV (±0.005% FSO).
VOLTAGE
PRESSURE
FULL-SCALE (FS)
FULL-SPAN OUTPUT (FSO)
OFFSET
Figure 1. Typical Pressure-Sensor Output
VBR
T
VBR
IBR
RSTC
VDD
EDI
ECS
ECLK
TO/FROM
EXTERNAL EEPROM
EDO
EEPROM
INTERFACE
ADC
BDRIVE
12
16
OUTPUT
PGA
TEMPERATURE-
DEPENDENT VOLTAGE
OFFSET TC
DAC REFERENCE VOLTAGE
FSO TC
DAC
Σ
16
A = 1
Figure 2. Simplified Diagram of Temperature Error Correction
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