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參數(shù)資料
| 型號(hào)： | MAX1457AWI+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 0.1% Accurate Signal Conditioner for Piezoresistive Sensor Compensation |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | MAX1457AWI+ |
MAX1457
0.1%-Accurate Signal Conditioner
for Piezoresistive Sensor Compensation
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
1
28
Positive Sensor Input. Input impedance >1M
. Rail-to-rail input range.
2
29
Negative Sensor Input. Input impedance >1M
. Rail-to-rail input range.
3
30
Positive Input of General-Purpose Operational Amplifier
4
31
Negative Input of General-Purpose Operational Amplifier
—
4, 16,
22, 32
Not internally connected.
7
3
PGA Output Voltage. Connect a 0.1F capacitor from VOUT to VSS. High impedance when
MCS is low.
6
2
Sensor Excitation Current. This pin drives a nominal 0.5mA through the sensor.
5
1
Output of General-Purpose Operational Amplifier. High impedance when MCS is low.
12
9
Reference Input to FSO Linearity DAC. Normally tied to VOUT.
11
8
Buffered FSO Linearity DAC Output. Use a resistor (RLIN) greater than 100k, from LINOUT
to ISRC to correct second order FSO nonlinearity errors. Leave unconnected if not
correcting second order FSO nonlinearity errors.
10
7
Buffered Bridge Voltage (the voltage at BDRIVE). Leave unconnected if unused.
9
6
Buffered FSO TC DAC Output. Tie to ISRC with a resistor (RSTC ≥ 50k).
8
5
Current-Source Reference. Connect a 50k
resistor from ISRC to VSS.
INP
INM
AMP+
AMP-
N.C.
VOUT
BDRIVE
AMPOUT
LINDACREF
LINOUT
VBBUF
FSOTCOUT
ISRC
13
10
FSO Linearity DAC Output Voltage. Connect 0.1F capacitor from LINDAC to VSS.
LINDAC
14
11
Negative Power Supply Input
VSS
15
12
OFFSET TC DAC Output Voltage. Connect a 0.1F capacitor from OTCDAC to VSS.
OTCDAC
16
13
FSO DAC Output Voltage. Connect a 0.1F capacitor from FSODAC to VSS.
FSODAC
17
14
FSO TC DAC Output Voltage. Connect a 0.1F capacitor from FSOTCDAC to VSS.
FSOTCDAC
18
15
OFFSET DAC Output Voltage. Connect a 0.1F capacitor from OFSTDAC to VSS.
OFSTDAC
19
17
Serial Input (data from EEPROM), active high. CMOS logic-level input pin through which the
MAX1457’s internal registers are updated with EEPROM coefficients. Disabled when MCS is
low.
EDO
20
18
Serial Output (data to EEPROM), active high. CMOS logic-level output pin through which
the MAX1457 gives external commands to the EEPROM. Temperature-compensation data
is available through this pin. Becomes high impedance when MCS is low.
EDI
21
19
CMOS Logic-Level Clock Output for external EEPROM. High impedance when MCS is low.
ECLK
22
20
Chip-Select Output for external EEPROM. CMOS logic-level output pin through which the
MAX1457 enables/disables EEPROM operation. High impedance when MCS is low.
ECS
23
21
Frequency Output. Internal oscillator output signal. Normally left open.
FOUT
24
23
Frequency Adjust. Connect to VSS with a 1.5M resistor (ROSC) to set internal oscillator fre-
quency to 100kHz. Connect a 0.1F bypass capacitor from FADJ to VSS.
FADJ
PIN
FUNCTION
NAME
25
24
Master Chip Select. The MAX1457 is selected when MCS is high. Leave unconnected for
normal operation (internally pulled up to VDD with 1M resistor). External 5k pull-up may
be required in noisy environments.
MCS
26
25
Bias Setting Pin. Connect to VDD with a 400k resistor (RBIAS). Connect a 0.1F bypass
capacitor from NBIAS to VSS.
NBIAS
27
26
Mid-Supply Reference for Analog Circuitry. Connect a 0.1F capacitor from VSS to AGND.
AGND
28
27
Positive Power-Supply Input. Connect a 0.1F capacitor from VDD to VSS.
VDD
TQFP
SO
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