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參數(shù)資料
| 型號(hào)： | MAX144BEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 108KSPS 8-UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 108k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 2 個(gè)單端，單極 |
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MAX144/MAX145
fication, and the first four data bits starting with the
MSB. The second 8-bit data stream contains the
remaining bits, D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX144/MAX145 support a maxi-
mum fSCLK of 2.17MHz. The QSPI circuit in Figure 9a
can be programmed to perform a conversion on each
of the two channels for the MAX144. Figure 9b shows
the QSPI interface timing.
PIC16 with SSP Module and PIC17 Interface
The MAX144/MAX145 are compatible with a PIC16/
PIC17 controller (C), using the synchronous serial-port
(SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 2 and 3.
In SPI mode, the PIC16/PIC17 Cs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings (Figure 10b)
are necessary to obtain the entire 12-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the C on SCLK’s rising edge.
The first 8-bit data stream contains three leading ones,
the channel identification, and the first four data bits
starting with the MSB. The second 8-bit data stream
contains the remaining bits, D7 through D0.
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin MAX
12
______________________________________________________________________________________
CHID
D11
D10
D9
D8
1
2
3
4
5
6
7
8
9
10
11
121314
15
16
D7
D6
D5
D4
D3
HIGH-Z
DOUT
CS/SHDN
SCLK
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
MSB
LSB
D2
D1
D0
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
CS/SHDN
SCLK
DOUT
CS
SCK
MISO
VDD
SS
QSPI
MAX144
MAX145
Figure 9a. QSPI Connections
Table 2. Detailed SSPCON Register Contents
CONTROL BIT
MAX144/MAX145
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT7
X
Write Collision Detection Bit
SSPOV
BIT6
X
Receive Overflow Detect Bit
CKP
BIT4
0
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM2
BIT2
0
SSPM1
BIT1
0
SSPM0
BIT0
1
SSPM3
BIT3
0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
fCLK = fOSC / 16.
SSPEN
BIT5
1
Synchronous Serial-Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
X = Don’t care
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