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參數(shù)資料
| 型號： | MAX144BEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 108KSPS 8-UMAX |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 108k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
DOUT valid timing characteristic. Data should be
clocked into the P on SCLK’s rising edge.
4) Pull CS/SHDN high at or after the 16th falling clock
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the LSB.
5) With CS/SHDN high, wait at least 60ns (tCS) before
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
Data can be output in two 8-bit sequences or continu-
ously. The bytes will contain the result of the conversion
padded with three leading ones and the channel identi-
fication before the MSB. If the serial clock hasn’t been
idled after the last LSB and CS/SHDN is kept low,
DOUT sends trailing zeros.
SPI and MICROWIRE Interface
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c).
Two consecutive 8-bit readings are necessary to obtain
the entire 12-bit result from the ADC. DOUT data transi-
tions on the serial clock’s falling edge and is clocked
into the P on SCLK’s rising edge. The first 8-bit data
stream contains three leading ones, the channel identi-
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin MAX
______________________________________________________________________________________
11
CS/SHDN
SCLK
DOUT
tCL
tDV
tCH
tSCLKS
HIGH-Z
tCS
tDO
tTR
Figure 7. Detailed Serial-Interface Timing Sequence
MAX144
MAX145
CS/SHDN
SCLK
DOUT
I/O
SK
SI
MICROWIRE
CS/SHDN
SCLK
DOUT
I/O
SCK
MISO
VDD
SS
MAX144
MAX145
SPI
Figure 8a. SPI Connections
8b. MICROWIRE Connections
CHID
D11
D10
D9
D8
1
2
3
4
5
6
7
8
9
10
11
121314
15
16
D7
D6
D5
D4
D3
HIGH-Z
DOUT*
CS/SHDN
SCLK
1ST BYTE READ
2ND BYTE READ
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
MSB
LSB
D2
D1
D0
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
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