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參數(shù)資料
| 型號： | MAX144BEUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 108KSPS 8-UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 108k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極 |
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin MAX
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS (Figure 7)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1F capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH-= GND
for MAX145, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Wake-Up Time
2.5
s
CS/SHDN Fall to Output Enable
tDV
CL = 100pF
120
ns
CS /SHDN Rise to Output Disable
tTR
CL = 100pF, Figure 1
120
ns
SCLK Fall to Output Data Valid
tDO
CL = 100pF, Figure 1
20
120
ns
External clock
0.1
2.17
SCLK Clock Frequency
fSCLK
Internal clock, SCLK for data transfer only
0
5
MHz
External clock
215
SCLK Pulse Width High
tCH
Internal clock, SCLK for data transfer only
(Note 8)
50
ns
External clock
215
SCLK Pulse Width Low
tCL
Internal clock, SCLK for data transfer only
(Note 8)
50
ns
SCLK to
CS /SHDN Setup
tSCLKS
60
ns
CS /SHDN Pulse Width
tCS
60
ns
Note 1: Tested at VDD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: "On" channel is grounded; sine wave applied to "off" channel (MAX144 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to VDD (MAX145 only).
Note 7: ADC performance is limited by the converter’s noise floor, typically 300Vp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as VFS(2.7V) -VFS(5.25V).
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