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參數(shù)資料
| 型號： | MAX1124EGK+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT LVDS/PAR 68QFN-EP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 250M |
| 數(shù)據(jù)接口： | LVDS，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 657mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個差分，單極 |
MAX1124
with an LVDS-compatible clock to achieve the best
dynamic performance. The clock signal source must be
a high-quality, low phase noise to avoid any degrada-
tion in the noise performance of the ADC. The clock
inputs (CLKP, CLKN) are internally biased to 1.2V,
accept a differential signal swing of 0.2VP-P to 1.0VP-P
and are usually driven in AC-coupled configuration.
See the
Differential, AC-Coupled Clock Input in the
Applications Information section for more circuit details
on how to drive CLKP and CLKN appropriately.
Although not recommended, the clock inputs also
accept a single-ended input signal.
The MAX1124 also features an internal clock manage-
ment circuit (duty-cycle equalizer) that ensures that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty cycle clock signal,
which desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock fre-
quency of >20MHz to work appropriately and accord-
ing to data sheet specifications.
Clock Outputs (DCLKP, DCLKN)
The MAX1124 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
2.1ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
Divide-by-2 Clock Control (CLKDIV)
The MAX1124 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that only operate with update rates one-half of the con-
verter’s sampling rate. Connecting CLKDIV to OVCC
allows data to be updated at the speed of the ADC input
clock.
System Timing Requirements
Figure 4 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1124 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of nine clock cycles.
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
12
______________________________________________________________________________________
INP ANALOG
VOLTAGE LEVEL
INN ANALOG
VOLTAGE LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY
DIGITAL OUTPUT CODE
(D9–D0)
TWO’S COMPLEMENT
DIGITAL OUTPUT CODE
(D9–D0)
> VCM + 0.3125V
< VCM - 0.3125V
1 (0)
11 1111 1111
(exceeds positive full scale,
OR set)
01 1111 1111
(exceeds positive full scale,
OR set)
VCM + 0.3125V
VCM - 0.3125V
0 (1)
11 1111 1111
(represents positive full
scale)
01 1111 1111
(represents positive full
scale)
VCM
0 (1)
10 0000 0000 or
01 1111 1111
(represents midscale)
00 0000 0000 or
11 1111 1111
(represents midscale)
VCM - 0.3125V
VCM + 0.3125V
0 (1)
00 0000 0000
(represents negative full
scale)
10 0000 0000
(represents negative full
scale)
< VCM - 0.3125V
> VCM + 0.3125V
1 (0)
00 0000 0000
(exceeds negative full scale,
OR set)
10 0000 0000
(exceeds negative full scale,
OR set)
Table 1. MAX1124 Digital Output Coding
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參數(shù)描述 |
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| MAX1124EGK-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1124EVKIT | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Evaluation Kit for the MAX1121 MAX1122 MAX1123 MAX1124 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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| MAX1125AIBH | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
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