參數(shù)資料
型號: MAX1124EGK+D
廠商: Maxim Integrated Products
文件頁數(shù): 15/17頁
文件大?。?/td> 0K
描述: IC ADC 10BIT LVDS/PAR 68QFN-EP
標準包裝: 30
位數(shù): 10
采樣率(每秒): 250M
數(shù)據(jù)接口: LVDS,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 657mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應商設備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸入數(shù)目和類型: 1 個單端,單極;1 個差分,單極
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________
7
SINAD vs. TEMPERATURE (fIN = 65.0344MHz,
fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124
toc19
TEMPERATURE (°C)
SINAD
(dB)
60
35
10
-15
60
59
58
57
56
55
54
53
52
51
50
-40
85
SFDR vs. TEMPERATURE (fIN = 65.0344MHz,
fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
MAX1124
toc20
TEMPERATURE (°C)
SFDR
(dBc)
60
35
10
-15
55
60
65
70
75
80
50
-40
85
POWER DISSIPATION vs. fSAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1124
toc21
fSAMPLE (MHz)
P
DISS
(mW)
170
130
90
50
445
435
465
455
485
475
495
505
425
10
250
210
FS VOLTAGE vs. FS ADJUST RESISTOR
MAX1124
toc22
FS ADJUST RESISTOR (
Ω)
V
FS
(V)
900
800
600 700
200 300 400 500
100
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.16
0
1000
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND AGND
RESISTOR VALUE APPLIED
BETWEEN REFADJ AND REFIO
FIGURE 6
SNR vs. VOLTAGE SUPPLY
(fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1124
toc23
VOLTAGE SUPPLY (V)
SNR
(dB)
2.0
1.9
1.8
1.7
1.6
60
59
58
57
56
55
54
53
52
51
50
1.5
2.1
AVCC = OVCC
INTERNAL REFERENCE vs. SUPPLY VOLTAGE
(fSAMPLE = 250.0057MHz)
MAX1124
toc24
SUPPLY VOLTAGE (V)
V
REFIO
(V)
2.0
1.9
1.8
1.7
1.6
1.2310
1.2320
1.2330
1.2340
1.2350
1.2300
1.5
2.1
MEASURED AT THE REFIO PIN
REFADJ = AVCC = OVCC
0.0E+00
1.0E+04
3.0E+04
2.0E+04
4.0E+04
5.0E+04
6.0E+04
7.0E+04
8.0E+04
507
295
508
509
510
511
43
NOISE HISTOGRAM
(DC INPUT, 128k-POINT DATA RECORD)
MAX1124
toc25
DIGITAL OUTPUT NOISE
CODE
COUNTS
fSAMPLE = 250MHz
56333
74401
PROPAGATION DELAY TIMES
vs. TEMPERATURE
MAX1124
toc26
TEMPERATURE (°C)
PROPAGATION
DELAY
(ns)
60
35
10
-15
1
2
3
4
5
6
0
-40
85
tCPDL
tPDL
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, VAGND = VOGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1F capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
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