參數(shù)資料
型號(hào): MAX1104EUA+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/17頁
文件大?。?/td> 0K
描述: IC CODEC 8BIT 8-UMAX
標(biāo)準(zhǔn)包裝: 2,500
類型: 通用
數(shù)據(jù)接口: *
分辨率(位): 8 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 59 / 55
電壓 - 電源,模擬: 2.7 V ~ 5.5 V
電壓 - 電源,數(shù)字: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
MAX1102/MAX1103/MAX1104
Configuring the ADC
When configuring the ADC immediately following
power-up, the first control word enables the ADC and
sets the T/H to track mode. Then wait 200s for the
internal reference to stablize (3s typical from standby
mode). Finally, the second control word sets the ADC
into either single or continuous mode and causes con-
version to take place.
Conversion Modes
The MAX1102/MAX1103/MAX1104 have two conver-
sion modes, single and continuous.
In single conversion mode (C0 = 0), a control word
must be written before an ADC conversion result can
be read, or DAC input data is accepted. Once a con-
version has occurred, the device will ignore any input
until a new control word is written. Figures 5 and 6
show the DAC and ADC single conversion mode timing
diagrams.
In continuous conversion mode (C0 = 1), the device
maintains its configuration from a single control word,
and continuously updates the ADC conversion result,
or accepts new DAC input data.
When operating the ADC and DAC simultaneously,
both converters must be in the same conversion mode.
ADC Single Conversion Mode
Set C0 = 0 to select single conversion mode. The
falling edge of SCLK after the eighth bit of each control
word causes the ADC to switch from track to hold
mode and begin conversion. To avoid corruption of the
conversion result, SCLK must be disabled for 36s
(Figure 6). After completing the conversion, the ADC
automatically returns to track mode, and the next eight
clock cycles shift out the result on DOUT.
A minimum of 3.5s in track mode is required for com-
plete acquisition.
8-Bit CODECs
12
______________________________________________________________________________________
SCLK
S
DAC
ADDR
DAC ON
S
DAC
ADDR
DAC ON
S
DAC
ADDR
DAC ON
S
DAC
ADDR
DAC ON
S
DAC
ADDR
DAC OFF
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DAC
DATA
DIN
OUT
NOTE: "S" DENOTES THE BEGINNING OF A CONTROL WORD
CS
Figure 5. DAC Single Conversion Mode Timing Diagram
SCLK
AIN
DOUT
MSB
1
2
3
4
tCONV
LSB
ACQUISITION MODE
ACQUISITION
MODE
MSB LSB
CS
SS
ADC
ADDR
ADC ON
S
ADC
ADDR
ADC ON
S
ADC
ADDR
ADC ON
S
ADC
ADDR
ADC ON
S
ADC
ADDR
ADC OFF
ADC
ON
CONVERSION
RESULT FOR 1
CONVERSION
RESULT FOR 2
CONVERSION
RESULT FOR 3
CONVERSION
RESULT FOR 4
S
ADC
ON
DIN
Figure 6. ADC Single Conversion Mode Timing Diagram
相關(guān)PDF資料
PDF描述
VI-2WB-CV-S CONVERTER MOD DC/DC 95V 150W
VE-2WL-CV-S CONVERTER MOD DC/DC 28V 150W
VE-2WJ-CV-S CONVERTER MOD DC/DC 36V 150W
VE-2WH-CV-S CONVERTER MOD DC/DC 52V 150W
VE-2WD-CV-S CONVERTER MOD DC/DC 85V 150W
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