參數(shù)資料
型號: MAX1104EUA+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/17頁
文件大?。?/td> 0K
描述: IC CODEC 8BIT 8-UMAX
標準包裝: 2,500
類型: 通用
數(shù)據(jù)接口: *
分辨率(位): 8 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調變:
動態(tài)范圍,標準 ADC / DAC (db): 59 / 55
電壓 - 電源,模擬: 2.7 V ~ 5.5 V
電壓 - 電源,數(shù)字: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-uMAX
包裝: 帶卷 (TR)
LSB of the control word. Successive conversions are
initiated after the last bit of the previous conversion
result has been clocked out. Resultant data is only
available after conversion is complete.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. This time, tACQ2, is cal-
culated by the following equation:
tACQ2 = (6.2 RS 15pF) + tACQ
where RS = the source impedance of the input signal;
tACQ is the T/H acquisition time from the Electrical
Characteristics table.
Conversion Progress
The comparator’s negative input is connected to the
auto-zero rail. Since the device requires only a single
supply, the ZERO node at the input of the comparator
equals VDD/2. The capacitive DAC restores node ZERO
to have no voltage difference at the comparator inputs
within the limits of an 8-bit resolution.
Input Voltage Range
Internal protection diodes that clamp the analog input
to VDD and GND allow AIN to swing from (VGND - 0.3V)
to (VDD + 0.3V) without damaging the device.
However, for accurate conversions, the input must not
exceed (VDD + 0.05V) or be less than (VGND - 0.05V).
The valid input range for the analog input is from GND
to VREF. The output code is invalid (code zero) when a
negative input voltage is applied, and full scale (FS)
when the input voltage exceeds the reference.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.5MHz full-
power bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, low-pass filters such as the MAX7418–
MAX7426 are recommended.
Digital-to-Analog Converter
The MAX1102/MAX1103/MAX1104 DAC section uses
an R-2R ladder network that converts the 8-bit digital
input into an equivalent analog output voltage propor-
tional to the applied reference voltage (Figure 3). The
DAC features a double-buffered input, and a buffered
analog output.
MAX1102/MAX1103/MAX1104
8-Bit CODECs
_______________________________________________________________________________________
9
AIN
HOLD
TRACK
5pF
TRACK
ZERO
CAPACITIVE
DAC
VDD/2
VREF
GND
15pF
MAX1102
MAX1103
MAX1104
2R
R
2R
REF
GND
NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FFhex.
DAC_ REGISTER
OUT
MSB
LSB
2R
R
2R
Figure 2. Equivalent Input Circuit
Figure 3. DAC Simplified Circuit Diagram
相關PDF資料
PDF描述
VI-2WB-CV-S CONVERTER MOD DC/DC 95V 150W
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