參數(shù)資料
型號: MAX11043ATL+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 4-Channel, 16-Bit, Simultaneous Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC; Package: THIN QFN, 40 pin ; Temperature Range: -40°C to +125°C
中文描述: 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, QCC40
封裝: 6 X 6 MM, ROHS COMPLIANT, TQFN-40
文件頁數(shù): 13/33頁
文件大?。?/td> 808K
代理商: MAX11043ATL+
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
20
______________________________________________________________________________________
SCHAN_<4:1>: Automatic ADC result output for each
channel (A, B, C, and D).
1 = ADC channel data is output on DOUT each time a
new result is valid in the sequence, A, B, C, and D.
0 = ADC data is not presented automatically for this
channel (default).
When SCHAN_ = 1, the selected ADC channel data is
automatically presented on DOUT each time
EOC
asserts low in the sequence A, B, C, and D with the
unselected channels omitted. The data transitions on
the rising edge of SCLK. Force
CS low to initiate trans-
mission.
CS can go high between results. The MSB of
the first selected ADC channel outputs immediately
after the falling edge of
EOC. EOC goes high after the
last bit of the selected channels clocks out or one clock
cycle before the next result is ready. Insufficient SCLK
pulses result in truncated data. Extra clock pulses give
an undefined output. In scan mode, keep DIN high or
write data to the MAX11043 as usual. In scan mode,
the MAX11043 ignores requests for data reads.
DECSEL<0>: Decimate select.
1 = decimate by 12.
0 = decimate by 24 (default).
Set DECSEL high to decimate the ADC result by 12,
doubling the number of samples. The SPI interface is
limited to 40Mbps.
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
X
DAC11
DAC10
DAC9
DAC8
Fine DAC Register (09h)
X<15:12>: Don’t-care bits.
DAC_<11:0>: Contains current fine DAC output value.
When using the DACSTEP input to change the DAC
value, this register updates to the new value on the
next rising edge of the system clock following the rising
edge of DACSTEP. The power-on default is 0.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
X
DACSTEP11
DACSTEP10
DACSTEP9
DACSTEP8
DACSTEP Register (0Ah)
X<15:12>: Don’t-care bits.
DACSTEP11:DACSTEP0<11:0>: Provides the size of
the DAC step. The value is positive only and the
UP/
DWN input is used to set the direction. The value in
the fine DAC register updates on the next rising edge
of the system clock following the rising edge of the
DACSTEP input. The power-on default is 0.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DACSTEP7
DACSTEP6
DACSTEP5
DACSTEP4
DACSTEP3
DACSTEP2
DACSTEP1
DACSTEP0
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
DACH7
DACH6
DACH5
DACH4
DACH3
DACH2
DACH1
DACH0
Coarse DACH/DACL Register (0Bh)
DACH7:DACH0<15:8>: High coarse DAC value.
DACL7:DACL0<7:0>: Low coarse DAC value.
Coarse DAC sets high and low references for the fine
DAC. The power-on default is 0.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DACL7
DACL6
DACL5
DACL4
DACL3
DACL2
DACL1
DACL0
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MAX11043ATL+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 4Ch Simul-Samp w/PGA & 8/12Bit D-S RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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