參數(shù)資料
型號(hào)： MAQ31753FXXXX
廠商： DYNEX SEMICONDUCTOR LTD
元件分類(lèi)： DMA控制器
英文描述： 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
封裝： QFP-84
文件頁(yè)數(shù)： 29/31頁(yè)
文件大小： 238K
代理商： MAQ31753FXXXX
MA31753
7/31
4.2 REMAINING WORD REGISTERS
Read access only. These 16-bit registers store the number of words left to be transferred for each area.
4.3 CURRENT ADDRESS REGISTERS
Read access only. These 16-bit registers store the addresses of the current words to be transferred to / from the area
represented by the register.
4.4 CURRENT PB / PS / AS REGISTER
Read access only. These 16-bit registers store the current page bank, address and process state information for each area.
When the areas have been selected within the IO space, PB, PS and AS shall be zero.
4.5 STATUS REGISTERS
CA
0: Channel not active
1: Channel active
This bit is automatically set to zero at an error or EOT condition.
EOT
0: Channel EOT not reached
1: Channel EOT reached.
CRQP
0: No channel DMA request pending.
1: Channel DMA request pending.
It is not possible to reset this bit as long as a DREQN line is asserted.
IPE
0: No internal parity error
1: Internal parity error when reading DMA register with parity.
BLE
0: No error
1: Block length error (odd block length in double word mode)
BIE
0: No error
1: Bus interface timeout error (caused either by not deasserting DREQN in handshake mode or by a bus timeout)
CLE
0: No error
1: CPU latched error (either MPROEN, EXADEN or PEN)
Interval
The interval, in CLK cycles, between each DMA request generated during area to area transfers.
Current Block Counter
D0
D15
Current Address
D0
D15
OIN
PB0
PB3 PS0
PS3 AS0
AS3
D0
D15
CA EOT CRQP
IPE BLE
BIE CLE
Interval
D0
D15
相關(guān)PDF資料
PDF描述
MAR31753FXXXX 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
MAS31753FXXXX 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
MAR28155CXXXX 24 I/O, PIA-GENERAL PURPOSE, CDIP40
MAR28155LXXXX 24 I/O, PIA-GENERAL PURPOSE, CQCC44
MAS28155CXXXX 24 I/O, PIA-GENERAL PURPOSE, CDIP40
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