參數(shù)資料
型號: MAQ31753FXXXX
廠商: DYNEX SEMICONDUCTOR LTD
元件分類: DMA控制器
英文描述: 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
封裝: QFP-84
文件頁數(shù): 2/31頁
文件大小: 238K
代理商: MAQ31753FXXXX
MA31753
10/31
5.4 AREA 1 AND 2 PB, PS AND AS
These readable and writable registers store the Page Bank, Processor and Address State information to be used when
accessing areas 1 and 2. When areas are defined within IO space, PB, PS and AS are set to zero.
5.5 TRANSFER INTERVAL
This readable and writable register gives the number of CLK cycles between each DMA request generated during area to
area transfers. The number entered as the interval value corresponds to a clock cycle interval increasing by 32 as follows:
0
=>
- (externally triggered DMA requests)
1
=>
0 (continuous DMA requests until the block is completed.
2=>
32
3=>
64
4=>
96
..
14
=>
416
15
=>
448
This function is valid only for transfers on channels 0 and 1. Channels 2 and 3 work ony only on externally triggered requests.
5.6 CONFIGURATION WORD
The DMA controller snoops the system address bus for the XIO address 0x8410. When this appears, the DMA stores the data
bus (qualified by DSN low) in an internal copy of the CPU configuration word.
OIN
PB0
PS0
AS0
PB3
PS3
AS3
D0
D15
Interval
D0
D15
相關(guān)PDF資料
PDF描述
MAR31753FXXXX 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
MAS31753FXXXX 4 CHANNEL(S), 16 MHz, DMA CONTROLLER, CQFP84
MAR28155CXXXX 24 I/O, PIA-GENERAL PURPOSE, CDIP40
MAR28155LXXXX 24 I/O, PIA-GENERAL PURPOSE, CQCC44
MAS28155CXXXX 24 I/O, PIA-GENERAL PURPOSE, CDIP40
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