參數(shù)資料
型號(hào): MACH131SP-7YI
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: High-Performance EE CMOS Programmable Logic
中文描述: EE PLD, 5.5 ns, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 6/48頁(yè)
文件大小: 1136K
代理商: MACH131SP-7YI
14
MACH 1 & 2 Families
initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset
delay time has elapsed.
SECURITY BIT
A security bit is provided on the MACH devices as a deterrent to unauthorized copying of the array
conguration patterns. Once programmed, this bit defeats readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. Programming and
verication are also defeated by the security bit. The bit can only be reset by erasing the entire
device.
相關(guān)PDF資料
PDF描述
MACH120-12JC High-Performance EE CMOS Programmable Logic
MACH120-15JC High-Performance EE CMOS Programmable Logic
MACH120-12 High-Performance EE CMOS Programmable Logic
MACH131SP-12YC High-Performance EE CMOS Programmable Logic
MACH131SP-15YC High-Performance EE CMOS Programmable Logic
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