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參數(shù)資料
| 型號： | MACH131SP-7YI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 5.5 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 18/48頁 |
| 文件大?。?/td> | 1136K |
| 代理商： | MACH131SP-7YI |
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MACH 1 & 2 Families
25
MACH111 AND MACH111SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
Parameter
Symbol
Parameter Description
-5
-7
-10
-12
-14
-15
-18
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tPD
Input, I/O, or Feedback to Combinatorial Output
5
7.5
10
12
14
15
18
ns
tS
Setup Time from Input, I/O, or Feedback
to Clock
D-type
3.5
5.5
6.5
7
8.5
10
12
ns
T-type
4
6.5
7.5
8
10
11
13.5
ns
tH
Register Data Hold Time
0000000
ns
tCO
Clock to Output
3.5
5
6
8
10
12
ns
tWL
Clock Width
LOW
2.5
35666
7.5
ns
tWH
HIGH
2.5
35666
7.5
ns
fMAX
Maximum
Frequency
External
Feedback
1/(tS + tCO)
D-type
143
95
80
66.7
54
50
42
MHz
T-type
133
87
74
62.5
50
47.6
39
MHz
Internal Feedback (fCNT)
D-type
182
133
100
76.9
69
66.6
53
MHz
T-type
167
125
91
71.4
57
55.5
44
MHz
No Feedback 1/(tWL + tWH)
200
167
100
83.3
66.7
MHz
tAR
Asynchronous Reset to Registered Output
7.5
9.5
11
16
19.5
20
24
ns
tARW
Asynchronous Reset Width (Note 2)
4.5
5
7.5
12
14.5
15
18
ns
tARR
Asynchronous Reset Recovery Time (Note 2)
4.5
5
7.5
8
10
12
ns
tAP
Asynchronous Preset to Registered Output
7.5
9.5
11
16
19.5
20
24
ns
tAPW
Asynchronous Preset Width (Note 2)
4.5
5
7.5
12
14.5
15
18
ns
tAPR
Asynchronous Preset Recovery Time (Note 2)
4.5
5
7.5
8
10
12
ns
tEA
Input, I/O, or Feedback to Output Enable
7.5
9.5
10
12
14.5
15
18
ns
tER
Input, I/O, or Feedback to Output Disable
7.5
9.5
10
12
14.5
15
18
ns
tLP
tPD Increase for Powered-down Macrocell (Note 3)
10
ns
tLPS
tS Increase for Powered-down Macrocell (Note 3)
7777777
ns
tLPCO
tCO Increase for Powered-down Macrocell (Note 3)
3333333
ns
tLPEA
tEA Increase for Powered-down Macrocell (Note 3)
10
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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| MACH210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:44 pin QFP socket/28 pin DIP 0.6” plug |
| MACH210-12 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH21012JC | 制造商:AMD 功能描述:* |
| MACH210-12JC | 制造商:Advanced Micro Devices 功能描述:COMPLEX-EEPLD, 64-CELL, 12NS PROP DELAY, 44 Pin, Plastic, PLCC |
| MACH210-12JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
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