- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄180472 > MACH131SP-7YI (LATTICE SEMICONDUCTOR CORP) High-Performance EE CMOS Programmable Logic PDF資料下載
參數(shù)資料
| 型號(hào)： | MACH131SP-7YI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 5.5 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 1/48頁 |
| 文件大?。?/td> | 1136K |
| 代理商： | MACH131SP-7YI |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Publication# 14051
Rev: K
Amendment/0
Issue Date: November 1998
MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
x
High-performance electrically-erasable CMOS PLD families
x
32 to 128 macrocells
x
44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
x
SpeedLocking – guaranteed xed timing up to 16 product terms
x
Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD
x
Congurable macrocells
— Programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type ip-ops
— Output Enables
— Choice of clocks for each ip-op
— Input registers for MACH 2 family
x
JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
x
Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
x
Safe for mixed supply voltage system designs
x
Bus-Friendly inputs and I/Os reduce risk of unwanted oscillatory outputs
x
Programmable power-down mode results in power savings of up to 75%
x
Supported by Vantis DesignDirect software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
x
Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO (formerly known as MACHPRO) software for in-system programmability
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACH120-12JC | High-Performance EE CMOS Programmable Logic |
| MACH120-15JC | High-Performance EE CMOS Programmable Logic |
| MACH120-12 | High-Performance EE CMOS Programmable Logic |
| MACH131SP-12YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-15YC | High-Performance EE CMOS Programmable Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:44 pin QFP socket/28 pin DIP 0.6” plug |
| MACH210-12 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
| MACH21012JC | 制造商:AMD 功能描述:* |
| MACH210-12JC | 制造商:Advanced Micro Devices 功能描述:COMPLEX-EEPLD, 64-CELL, 12NS PROP DELAY, 44 Pin, Plastic, PLCC |
| MACH210-12JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:High-Density EE CMOS Programmable Logic |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。