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參數(shù)資料
| 型號： | MAC7121VVF |
| 廠商： | Motorola, Inc. |
| 英文描述： | MAC7100 Microcontroller Family Hardware Specifications |
| 中文描述： | MAC7100微控制器系列硬件規(guī)格 |
| 文件頁數(shù)： | 30/48頁 |
| 文件大?。?/td> | 1514K |
| 代理商： | MAC7121VVF |
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30
MAC7100 Microcontroller Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Electrical Characteristics
3.11 Serial Peripheral Interface Electrical
Specifications
3.11.1 Master Mode
Figure 11 and Figure 12 illustrate master mode timing. Timing values are shown in Table 33.
Table 33. SPI Master Mode Timing Characteristics
1
3.11.2 Slave Mode
Figure 13 and Figure 14 illustrate the slave mode timing. Timing values are shown in Table 34.
1
The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent
between the Master and the Slave timing shown in Table 34.
Conditions are shown in Table 6 unless otherwise noted, C
LOAD
= 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
1
/
4
2048
—
—
1024 t
bus
—
—
25
—
25
25
Unit
W1a P Operating Frequency
W1b P SCK Period t
sck
= 1/f
op
W2
D Enable Lead Time
W3
D Enable Lag Time
W4
D Clock (SCK) High or Low Time
W5
D Data Setup Time (Inputs)
W6
D Data Hold Time (Inputs)
W9
D Data Valid (after Enable Edge)
W10 D Data Hold Time (Outputs)
W11 D Rise Time Inputs and Outputs
W12 D Fall Time Inputs and Outputs
f
op
t
sck
t
lead
t
lag
t
wsck
t
su
t
hi
t
v
t
ho
t
r
t
f
DC
4
1
/
2
1
/
2
—
—
—
—
—
—
—
—
—
—
—
f
bus
t
bus
t
sck
t
sck
ns
ns
ns
ns
ns
ns
ns
t
bus
30
25
0
—
0
—
—
Table 34. SPI Slave Mode Timing Characteristics
Conditions are shown in Table 6 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
X1a
P Operating Frequency
f
op
t
sck
t
lead
t
lag
t
wsck
t
su
t
hi
t
a
t
dis
t
v
t
ho
t
r
t
f
DC
—
1
/
4
f
bus
t
bus
t
cyc
t
cyc
ns
X1b
P SCK Period t
sck
= 1/f
op
D Enable Lead Time
4
—
2048
X2
1
—
—
X3
D Enable Lag Time
1
—
—
X4
D Clock (SCK) High or Low Time
t
cyc
30
25
—
—
X5
D Data Setup Time (Inputs)
—
—
ns
X6
D Data Hold Time (Inputs)
25
—
—
ns
X7
D Slave Access Time
—
—
1
t
cyc
t
cyc
ns
X8
D Slave SIN Disable Time
—
—
1
X9
D Data Valid (after SCK Edge)
—
—
25
X10
D Data Hold Time (Outputs)
0
—
—
ns
X11
D Rise Time Inputs and Outputs
—
—
25
ns
X12
D Fall Time Inputs and Outputs
—
—
25
ns
F
Freescale Semiconductor, Inc.
n
.
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