參數(shù)資料
型號(hào)： MAC7121MAG50
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller Family Hardware Specifications
中文描述： 微控制器系列硬件規(guī)格
文件頁(yè)數(shù)： 16/56頁(yè)
文件大小： 471K
代理商： MAC7121MAG50
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Electrical Characteristics
Freescale Semiconductor
16
3.8.2
PLL Filter Characteristics
The oscillator provides the reference clock for the PLL as shown in
Figure 3
. The voltage controlled
oscillator (VCO) of the PLL is also the system clock source in self clock mode. In order to operate reliably,
care must be taken to select proper values for external loop filter components.
Figure 3. Basic PLL Functional Diagram
The procedure described below can be used to calculate the resistance and capacitance values using typical
values for K
1
,
f
1
and i
ch
from
Table 20
. First, the VCO Gain at the desired VCO output frequency is
approximated by:
Eqn. 8
The phase detector relationship is given by:
Eqn. 9
i
ch
is the current in tracking mode. The loop bandwidth
f
C
should be chosen to fulfill the Gardner’s stability
criteria by at least a factor of 10, a typical value for the stability factor is 50.
ζ
= 0.9 ensures a good transient
response.
Eqn. 10
And finally the frequency relationship is defined as:
Eqn. 11
With the above inputs the resistance can be calculated as:
Eqn. 12
The capacitance C
S
can now be calculated as:
Eqn. 13
Phase
Detector
1
REFDV+1
K
φ
f
REF
V
DD
PLL
R
C
P
C
S
K
V
Loop Divider
1
SYNR+1
f
VCO
f
OSC
1
2
f
CMP
VCO
Δ
K
V
K
1
e
1
K
1
1V
f
VCO
–
(
--f
)
=
K
Φ
i
ch
–
K
V
=
f
C
2
ζ
f
----------------------------------------
1
π
ζ
1
ζ
2
+
+
(
)
10
------
f
C
f
4 10
-------------
ζ
0.9
=
(
)
;
<
→
<
n
f
f
REF
----------
2
SYNR
1
+
(
)
=
=
R
2
π
n
f
C
K
Φ
---------------------------
=
C
S
ζ
2
π
f
C
R
---2
f
C
R
0.516
ζ
0.9
=
(
)
;
≈
=
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