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參數(shù)資料
| 型號： | M8813F3Y-90K1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 68/85頁 |
| 文件大小： | 601K |
| 代理商： | M8813F3Y-90K1T |
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M88 FAMILY
70/85
Table 51B. Write, Erase and Program Timing (3 V Range)
Note: 1. Any input used to select an internal M88x3Fxx FLASH+PS D function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timi ng as E, DS, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Symbol
Parameter
Condition s
-15
Unit
Min
Max
tLVLX
ALE or AS Pulse Width
28
tAVLX
Address Setup Time
(Note 1)
10
ns
tLXAX
Address Hold Time
(Note 1)
12
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1,3)
30
ns
tSLWL
CS Valid to Leading Edge of WR
(Note 3)
34
ns
tDVWH
WR Data Setup Time
(Note 3)
45
ns
tWHDX
WR Data Hold Time
(Note 3)
8ns
tWLWH
WR Pulse Width
(Note 3)
48
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
0ns
tWHAX2
Trailing Edge of WR to DPLD Address Invalid
(Note 3,6)
0ns
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
45
ns
tDVMV
Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear
(Notes 3,5)
90
ns
tAVPV
Address Input Valid to Address
Output Delay
(Note 2)
48
ns
tWLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes 3,4)
90
ns
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