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參數(shù)資料
| 型號： | M8813F3Y-90K1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 32/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F3Y-90K1T |
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M88 FAMILY
38/85
80C31
Figure 22 shows the interface to the 80C31, which
has an 8-bit multiplexed address/data bus. The
lower address byte is multiplexed with the data
bus. The microcontroller control signals PSEN,
RD, and WR may be used for accessing the
internal memory components and I/O Ports. The
ALE input (pin PD0) latches the address.
80C251
The Intel 80C251 microcontroller features a user-
configurable bus interface with four possible bus
configurations, as shown in Table 21.
Configuration 1 is 80C31 compatible, and the bus
interface
to
the
M88x3Fxx
FLASH+PSD is
identical to that shown in Figure 22. Configurations
2 and 3 have the same bus connection as shown
in Figure 23. There is only one read input (PSEN )
connected to the Cntl1 pin on the M88x3Fxx
FLASH+PSD. The A16 connection to the PA0 pin
allows for a larger address input to the M88x3Fxx
FLASH+PSD. Configuration 4 is shown in Figure
24. The RD signal is connected to Cntl1 and the
PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes:
Page Mode and Non-Page Mode. In Non-Page
Mode, the data is multiplexed with the lower
address byte, and ALE is active in every bus cycle.
In Page Mode, data D[7:0] is multiplexed with
address A[15:8]. In a bus cycle where there is a
Page hit, the ALE signal is not active and only
addresses A[7:0] are changing. The M88x3Fxx
FLASH+PSD supports both modes. In Page
Mode, the PSD bus timing is identical to Non-Page
Mode except the address hold time and setup time
with respect to ALE is not required. The PSD
access time is measured from address A[7:0] valid
to data in valid.
80C51XA
The
Philips
80C51XA
microcontroller
family
supports an 8- or 16-bit multiplexed bus that can
Figu re 26. Interfacing the M88x3Fxx FLASH+PSD with a 68HC11
9
10
11
12
13
14
15
16
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0 (R_W)
CNTL1(E)
CNTL 2
PD0–AS
PD1
PD2
RESET
20
21
22
23
24
25
3
5
4
6
42
41
40
39
38
37
36
35
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A14
A15
A13
A11
A12
AD1
AD2
AD3
AD4
AD5
AD6
AD7
E
AS
R/W
XT
EX
RESET
IRQ
XIRQ
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC0
PC1
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
E
AS
R/ W
31
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
8
7
17
19
18
34
33
32
43
44
45
46
47
48
49
50
52
51
30
29
28
27
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
MODB
2
68HC11
M88x3Fxx
RESET
AD[7:0]
PC2
AI02884
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| M88141W-15T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-90K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
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