deveopmen
Rev.B2 for proof reading
Reset
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
27
(006B
16
)
(006C
16
)
(006D
16
)
(006E
16
)
(006F
16
)
(0070
16
)
(0071
16
)
(0072
16
)
(0073
16
)
(0074
16
)
(0075
16
)
(0076
16
)
(0077
16
)
(0078
16
)
(0079
16
)
(007A
16
)
(007B
16
)
(007C
16
)
(007D
16
)
(007E
16
)
(007F
16
)
(0081
16
)
(0086
16
)
(0088
16
)
(0089
16
)
(008A
16
)
(008B
16
)
(008C
16
)
(008D
16
)
(008E
16
)
(008F
16
)
(0090
16
)
(0091
16
)
(0004
16
)
(0005
16
)
(0006
16
)
(0007
16
)
(0008
16
)
(0009
16
)
(000A
16
)
(000B
16
)
(000C
16
)
(000D
16
)
(000E
16
)
(000F
16
)
(0010
16
)
(0011
16
)
(0012
16
)
(0014
16
)
(0015
16
)
(0016
16
)
(0017
16
)
(0018
16
)
(0019
16
)
(001A
16
)
(001B
16
)
(001C
16
)
(001D
16
)
(001E
16
)
(001F
16
)
(0040
16
)
(0041
16
)
(0057
16
)
(0068
16
)
(0069
16
)
(006A
16
)
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
Wait control register
Address match interrupt control register
Protect register
External data bus width control register
Main clock divided register
Oscillation stop detect register
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
Address match interrupt register 1
VDC control register for PLL
Address match interrupt register 2
VDD control register 1
Address match interrupt register 3
VDD control register 1
DRAM control register
DRAM refresh interval set register
Flash memory control register 0
DMA0 interrupt control register
Timer B5 interrupt control register
DMA2 interrupt control register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
80
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
16
UART2 receive /ACK interrupt control register
Timer A0 interrupt control register
UART3 receive/ACK interrupt control register
Timer A2 interrupt control register
UART4 receive/ACK interrupt control register
Timer A4 interrupt control register
UART0 receive/ACK interrupt control register
A-D0 interrupt control register
UART1 receive/ACK interrupt control register
Intelligent I/O interrupt control register 0
Timer B1 interrupt control register
Intelligent I/O interrupt control register 2
Timer B3 interrupt control register
Intelligent I/O interrupt control register 4
INT5 interrupt control register
Intelligent I/O interrupt control register 6
INT3 interrupt control register
Intelligent I/O interrupt control register 8
INT1 interrupt control register
A-D1 interrupt control register
DMA1 interrupt control register
UART2 transmit /NACK interrupt control register
DMA3 interrupt control register
UART3 transmit /NACK interrupt control register
Timer A1 interrupt control register
UART4 transmit /NACK interrupt control register
Timer A3 interrupt control register
UART2
bus collision detection interrupt
control register
UART0 transmit /NACK interrupt control register
20
16
FF
16
XXXX0 0 0 0
X00000XX
0000X000
XXXX0 0 0 0
XXXXX0 0 0
XXX0 1 0 0 0
16
0 00
00
16
00
16
00
16
XXX
XXXXXX01
XXXX 0 0 0
XX000 0 0 1
XXXX 0 0 0
XXXX 0 0 0
UART0/UART3
bus collision detection interrupt
control register
XXXX0 0 0
XXXX0 0 0
XXXX0 0 0
XXXX0 0 0
XXXX0 0 0
XXXX0 0 0
XXXX0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 00 0
XXXX 00 0
XXXX 00 0
XXXX 00 0
XXXX 00 0
XXXX 00 0
XXXX 00 0
XXXX 00 0
XX0 00 0 0
XX0 00 0 0
XX0 00 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
XXXX 0 0 0
UART1/UART4 bus collision detection
interrupt control register
XXXX 0 0 0
x : Nothing is mapped to this bit
: Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note 1: When the V
CC
level is applied to the CNV
SS
pin, it is 03
16
at a reset.
Note 2: When the BYTE pin is "L", bit 3 is "1". When the BYTE pin is "H", bit 3 is "0".
(Note 1)
(Note 2)
00
16
00
16
XXXX 0 0 0
Intelligent I/O interrupt control register 10/
CAN interrupt 1 control register
Intelligent I/O interrupt control register 11/
CAN interrupt 2 control register
Figure 1.4.3. Device's internal status after a reset is cleared (1/10)