參數(shù)資料
型號: M700000003
廠商: Spansion Inc.
英文描述: 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
中文描述: 2 × 64兆位(8米× 16位)的CMOS 3.0伏特,只有頁面模式閃存數(shù)據(jù)存儲128兆位(8米× 16位)的CMOS
文件頁數(shù): 76/128頁
文件大小: 918K
代理商: M700000003
74
Am70PDL127BDH/Am70PDL129BDH
November 25, 2003
A D V A N C E I N F O R M A T I O N
pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 25.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
66
85
t
WC
t
WP
t
CW
t
BW
t
AW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
t
CH
t
CEH
t
WEH
Write Cycle Time
Min
70
85
ns
Write Pulse Time
Min
50
60
ns
Chip Enable to End of Write
Min
60
70
ns
Data Byte Control to End of Write
Min
60
70
ns
Address Valid to End of Write
Min
60
70
ns
Address Setup Time
Min
0
ns
Write Recovery Time
Min
0
ns
WE# Low to Write to Output High-Z
Max
20
ns
WE# High to Write to Output Active
Min
0
ns
Data Set-up Time
Min
30
Data Hold from Write Time
Min
0
ns
CE2 Hold Time
Min
300
μs
Chip Enable High Pulse Width
Min
10
ns
Write Enable High Pulse Width
Min
6
ns
t
WC
t
WP
t
AW
t
WEH
t
WR
t
CW
t
BW
Valid Data In
t
AS
t
CH
t
OEW
Addresses
A20 to A0
WE#
CE#1s
CE2s
LB#, UB#
D
IN
DQ15 to DQ0
D
OUT
DQ15 to DQO
t
ODW
t
DS
t
DH
High-Z
(Note 1)
(Note 3)
(Note 4)
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