
M66222SP/FP
1 8-BIT
×
8-B 2 MAIL-BOX
×
2 MAIL-BOX
128
1
DESCRIPTION
The M66222 is a mail box that incorporates two complete CMOS
shared memory cells of 128
×
8-bit configuration using high-
performance silicon gate CMOS process technology, and are
equipped with two access ports of A and B.
Access ports A and B are equipped with independent addresses CS,
WE and OE control pins and I/O pins to allow independent and
asynchronous read/write operations individually. This product
exclusively performs a write operation from A port and a read operation
from B port for one memory, and a read operation from A port and a
write operation from B port for the other memory.
FEATURES
Memory configuration of 128
×
8 bits
×
2 memory areas
High-speed access, address access time 40ns (typ.)
Complete asynchronous accessibility from ports A and B
Fixed read/write access ports for memory
Completely static operation
Low power dissipation CMOS design
5V single power supply
TTL direct-coupled I/O
3-state output for I/O pins
APPLICATION
Inter-MCU data transfer memory, communication buffer memory
MIMITSUBISHI
DIDIGITAL ASSP
BLOCK DIAGRAM
PIN CONFIGURATION (Top view)
41
40
38
30
37
36
35
34
33
32
31
22
23
24
25
26
27
28
29
1
2
4
12
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
42
21
READ/
WRITE
CONTROL
CIRCUIT
MEMORY AREA(1)
128-WORD
×
8-BIT
CONFIGURATION
0-127
ADDRESSES
S
O
READ/
WRITE
CONTROL
CIRCUIT
ROW/COLUMN
DECODER
ROW/COLUMN
DECODER
MEMORY AREA(2)
128-WORD
×
8-BIT
CONFIGURATION
128-255
ADDRESSES
O
S
I
C
I
C
Write
Read
A
0
A~A
6
A
A
0
B~A
6
B
V
CC
GND
CSA
WEA
OEA
A
7
A
A
0
A
A
1
A
A
2
A
A
3
A
A
4
A
A
5
A
A
6
A
I/O
0
A
I/O
1
A
I/O
2
A
I/O
3
A
I/O
4
A
I/O
5
A
I/O
6
A
I/O
7
A
CSB
WEB
OEB
A
7
B
A
0
B
A
1
B
A
2
B
A
3
B
A
4
B
A
5
B
A
6
B
I/O
0
B
I/O
1
B
I/O
2
B
I/O
3
B
I/O
4
B
I/O
5
B
I/O
6
B
I/O
7
B
CHIP SELECT
INPUT
WRITE
ENABLE INPUT
OUTPUT
ENABLE INPUT
A PORT
ADDRESS
INPUT
A PORT
DATA I/O
CHIP
SELECT INPUT
WRITE
ENABLE INPUT
OUTPUT
ENABLE INPUT
B PORT
ADDRESS
INPUT
B PORT
DATA I/O
Read
Write
7
7
CSA
→
→
→
→
→
→
→
→
→
→
→
←
←
←
←
←
←
←
←
←
←
←
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
25
24
23
22
27
26
29
28
31
30
35
34
33
32
37
36
39
38
41
40
42
WEA
NC
OEA
I/O
7
A
GND
I/O
6
A
I/O
5
A
I/O
4
A
I/O
3
A
I/O
2
A
I/O
1
A
I/O
0
A
A
7
A
A
6
A
A
5
A
A
4
A
A
3
A
A
2
A
A
1
A
A
0
A
CSB
V
CC
NC
WEB
A
0
B
OEB
A
1
B
A
2
B
A
3
B
A
4
B
A
5
B
I/O
7
B
A
6
B
A
7
B
I/O
6
B
I/O
5
B
I/O
4
B
I/O
3
B
I/O
2
B
I/O
1
B
I/O
0
B
CHIP SELECT
INPUT
WRITE ENABLE
INPUT
OUTPUT ENABLE
INPUT
A PORT
ADDRESS
INPUT
A PORT
DATA I/O
CHIP SELECT
INPUT
WRITE ENABLE
INPUT
OUTPUT ENABLE
INPUT
B PORT
ADDRESS
INPUT
B PORT
DATA I/O
Outline
NC: No Connection
42P4B
42P2R-A
M