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參數(shù)資料
| 型號： | M65817AFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Digital Amplifier Processor of S-Master Technology |
| 中文描述： | 數(shù)字放大器處理器的S - Master技術(shù) |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 246K |
| 代理商： | M65817AFP |
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Digital Amplifier Processor of S-Master* Technology
M65817AFP
MITSUBISHI SOUND PROCESSOR ICs
MITSUBISHI
ELECTRIC
bit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Flag name
MODE1
MODE2
IMCKSEL
DSDFCO0
DSDFCO1
SYNC
XFsoOEN
ASYNCEN2
CHSEL
DRPOL
SRCRST
Functional Explanation
Mode setting1
Mode setting2
Input Master Clock Selection
H
L
INIT
-
-
L
L
L
L
L
L
L
L
L
-
L
L
L
L
L
L
L
L
L
L
L
L
"H" fixed
"L" fixed
256Fs
512Fs
Resynchronization
XfsoOUT
pin output "enable"
Asyncronous Detection Flag for secondary Side
L / R inversion of PWM output
Σ
Block: Rch Input Phase
Sampling Rate Converter Reset
disable
enable
active
enable
disable
non-active
Positive-phase
Non-active
Negative-phase
Active
GIMUTE
NSPMUTE
PGMUTE
NSSPEED
NSOBIT
DCDRPOL
DCDSEL0
DSDSEL1
ACDRPOL
ACDSEL0
ACDSEL1
ACDSEL2
Zero Mute at Gain Control Input Clock
Duty 50 percent Mute of PWM Output
G_MUTE of PWM Output Data
Σ
Block: Operation Speed
Σ
Block: Setting of Output Bit Number
Σ
Block: Rch Phase of DC dithering
Active
Active
Active
Non-active
Non-active
Non-active
"L" fixed
6 bits (63 value)
Positive-phase
5 bits (31 value)
Negative-phase
Σ
Block: Rch Phase of AC dithering
Negative-phase
Positive-phase
Table 3-1 Setting of Down Sampling Filter Coefficient
ROM1
ROM2
bit
Flag Name
L
4
DSDFCO0
L
5
DSDFCO1
Table 3-2 DC dithering Selection at
DS
Block
bit
Flag Name
19
DCDSEL0
20
DCDSEL1
Table 3-3 AC dithering Selection at
DS
Block
bit
Flag Name
22
ACDSEL0
23
ACDSEL1
24
ACDSEL2
Input Master Clock Selection (bit3:
IMCKSEL
).
"L":256Fs
"H":512Fs
Selection of of Down Sampling Filter Coefficient for SACD input (bi4,bit5: DSDFCO0,DSDFCO1) .
Refer to Table 6-3-1.
Resynchronization (bit6:
SYNC
).
Resynchronization function is same at
SYNC
pin's function. Refer to Operation Explanation, Chapter 5-1.10 .
Resynchronization process starts by SYNC rise edge,
therefore SYNC level must be fixed to "L"just before SYNC operation .
L->H : Resynchronization.
Refer to 6-3-2
Σ
Block: AC dithering selection
Refer to 6-3-3
Σ
Block: DC dithering Selection
don't care
Refer to Table 6-3-1.
Filter Coefficient of Down Sampling
ROM3
L
H
ROM4
H
H
H
L
Non-dithering
L
L
DC dithering
H
L
DC dithering
L
H
DC
H
H
Non-dithering
don't care
L
L
AC dithering A
L
H
L
AC dithering C
L
L
H
AC dithering E
L
H
H
3. System2 Mode (Secondary side).
"Enable" of
XfsoOUT
pin Output(bit7:
XfsoOEN
).
"L": Clock Output (enable), "H": L fixed (disable)
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相關(guān)代理商/技術(shù)參數(shù) |
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| M65818AFP | 制造商:Renesas Electronics Corporation 功能描述:M65818AFP |
| M65821 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:CD PLAYER DIGITAL SIGNAL PROCESSOR |
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| M65824AFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC |
| M65824FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A |
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