參數(shù)資料
型號(hào): M65817AFP
廠商: Mitsubishi Electric Corporation
英文描述: Digital Amplifier Processor of S-Master Technology
中文描述: 數(shù)字放大器處理器的S - Master技術(shù)
文件頁(yè)數(shù): 14/28頁(yè)
文件大?。?/td> 246K
代理商: M65817AFP
14
Digital Amplifier Processor of S-Master* Technology
M65817AFP
MITSUBISHI SOUND PROCESSOR ICs
MITSUBISHI
ELECTRIC
EXDATAL
and
EXDATAR
are data input pins under condition of `
External Sampling Rate Converter 8fs`
mode.
EXDATAL
and
EXDATAR
are changed to output pins for Sampling Rate Converter except condition of `External
Rate Converter 8fs` mode and
EXIOSEL
="H".
In case of un-using `External sampling rate converter 8fs` mode,
EXIOSEL
="L" and
EXBCK, EXWCK, EXDATAL
and
EXDATAR
must be tied to low position.
EXDATAL, EXDATAR, EXBCK
and
EXWCK
pin's input/output format is following figure.
Except `
External Rate
Converter 8fs`
mode
(Except MODE1,2=L,H)
EXDATAL,EXDATAR,EXBCK
and
EXWCK
input/output format
Multiplex and Single use
The primary clock side is not operated with synchronization, because internal Sampling Rate Converter is not used.
Under `
External Rate Converter 8fs
` mode, the primary clock side asynchronous detection operates as `forced-disable`.
The secondary clock side is operated with synchronization by
FsoCKO
pin.
Then, M65817AFP needs that rising edge of FsoCKO connected from M65817AFP to external sampling rate converter
and rising edge of
EXWCK
connected from external rate converter to M65817AFP are in synchronized phase.
Master
FsoCKO(Secondary Side)
Multiplex use ( 6ch )
Single use ( 2ch )
Input Signal Mode
EIOSEL
EXWCK,EXBCK,EXDATAL,EXDATAR
input/ output
`
External Rate
Converter 8fs`
mode
(MODE1,2=L,H)
L
input
H
input
L
input
H
output
MSB first left justified (24bit)
0
1
7
8
23
EXDATAL
/EXDATAR
9
20
21
22
EXWCK
EXBCK
MSB
LSB
8fso
256fso
LRCK
Fsil
Slave
Slave
LRCK
Fsil
LRCK
Fsil
FSoCKO
LRCK
Fsil
FsoI
FsoI
FsoI
Fsol
2. Setting on `External Rate Converter 8fs` Mode
2-1. EXBCK,EXWCK,EXDATAL,EXDATAR,EXIOSEL
2-2. SYNC,Fsol,Fsil,SFLAG
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